公开(公告)号：US20250087573A1

公开(公告)日：2025-03-13

申请号：US18464926

申请日：2023-09-11

Applicant: Applied Materials, Inc.

Inventor： Tyler Sherwood ,  Raghav Sreenivasan ,  Michael Chudzik ,  Maria Gorchichko

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/48 ,  H01L23/64

Abstract: The interconnect resistances in a hybrid bonded structure can be controlled and designed. The resistance of each interconnect can be controlled by the width of the vias, the number of vias, and the thickness of liners within the vias. A first interconnect and a second interconnect of a hybrid bonded structure can have different interconnect resistances despite being on the same wafer or chip. The techniques described herein include designing interconnects and forming interconnects with particular resistances.

公开(公告)号：US12055821B2

公开(公告)日：2024-08-06

申请号：US17100400

申请日：2020-11-20

Applicant: Applied Materials, Inc.

Inventor： Lan Yu ,  Benjamin D. Briggs ,  Tyler Sherwood ,  Zihao Yang

IPC: H01L21/66 ,  G02F1/1339 ,  H01L21/67 ,  H01L23/522 ,  H01L23/532 ,  H01L29/423 ,  H01L31/20 ,  H01L33/46 ,  H10K59/50 ,  H10N10/855 ,  G02F1/1335 ,  G02F1/1362 ,  H01L21/311

CPC classification number: G02F1/13394 ,  H01L21/67207 ,  H01L21/67225 ,  H01L22/26 ,  H01L23/5226 ,  H01L23/53219 ,  H01L23/53276 ,  H01L29/42368 ,  H01L31/206 ,  H01L33/46 ,  H01L33/465 ,  H10K59/50 ,  H10N10/855 ,  G02F1/133553 ,  G02F1/136227 ,  G02F1/136277 ,  H01L21/31122 ,  H01L2224/05181 ,  H01L2224/05184

Abstract: Processing methods may be performed to form a pixel isolation structure on a semiconductor substrate. The method may include forming a pixel isolation bilayer on the semiconductor substrate. The pixel isolation bilayer may include a high-k layer overlying a stopping layer. The method may include forming a lithographic mask on a first region of the pixel isolation bilayer. The method may also include etching the pixel isolation bilayer external to the first region. The etching may reveal the semiconductor substrate. The etching may form the pixel isolation structure.

公开(公告)号：US11705490B2

公开(公告)日：2023-07-18

申请号：US17169916

申请日：2021-02-08

Applicant: Applied Materials, Inc.

Inventor： Ashish Pal ,  El Mehdi Bazizi ,  Siddarth Krishnan ,  Xing Chen ,  Lan Yu ,  Tyler Sherwood

IPC: H01L21/02 ,  H01L29/36 ,  H01L29/872 ,  H01L29/66 ,  H01L21/285 ,  H01L21/3065 ,  H01L21/265

CPC classification number: H01L29/36 ,  H01L21/02164 ,  H01L21/26513 ,  H01L21/28537 ,  H01L21/3065 ,  H01L29/66143 ,  H01L29/872

Abstract: Exemplary methods of forming a semiconductor structure may include forming a doped silicon layer on a semiconductor substrate. A level of doping may be increased at an increasing distance from the semiconductor substrate. The methods may include etching the doped silicon layer to define a trench extending to the semiconductor substrate. The doped silicon layer may define a sloping sidewall of the trench. The trench may be characterized by a depth of greater than or about 30 μm. The methods may include lining the trench with a first oxide material. The methods may include depositing a second oxide material within the trench. The methods may include forming a contact to produce a power device.

公开(公告)号：US20220165912A1

公开(公告)日：2022-05-26

申请号：US17100402

申请日：2020-11-20

Applicant: Applied Materials, Inc.

Inventor： Lan Yu ,  Benjamin D. Briggs ,  Tyler Sherwood ,  Raghav Sreenivasan

IPC: H01L33/00 ,  G02F1/1362 ,  H01L33/62

Abstract: Processing methods may be performed to form a pixel material in a semiconductor substrate. The methods may include forming a lithographic mask overlying the semiconductor substrate. The lithographic mask may include a window. The method may include forming a via in the semiconductor substrate by a dry etch process through the window. The method may also include forming the pixel material by depositing a fill material in the via.

公开(公告)号：US20250079312A1

公开(公告)日：2025-03-06

申请号：US18460154

申请日：2023-09-01

Applicant: Applied Materials, Inc.

Inventor： Tyler Sherwood ,  Raghav Sreenivasan ,  Kun Li

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/00

Abstract: A structure for semiconductor devices having a high-dielectric constant dielectric film on the top surface of the structure can be used to form semiconductor devices that are composed of hybrid bonded structures with reduced dielectric surface area and reduced pitch for metal studs. For example, the dielectric constant of the dielectric film can be about or greater than 7 or 8. A semiconductor device can be formed by hybrid bonding the dielectric film of the structure to a dielectric film of a similar structure. A dielectric film-oxide-metal-substrate structure can be formed with the dielectric film on the top surface of the stack. A multi-material etch can be used etch features in the dielectric film and the oxide in a dielectric film-oxide-metal-substrate stack. A chemical-mechanical polishing technique can be used to precisely form the surface of the structure in preparation for hybrid bonding.

公开(公告)号：US11830824B2

公开(公告)日：2023-11-28

申请号：US17214411

申请日：2021-03-26

Applicant: Applied Materials, Inc.

Inventor： Amirhasan Nourbakhsh ,  Lan Yu ,  Joseph F. Salfelder ,  Ki Cheol Ahn ,  Tyler Sherwood ,  Siddarth Krishnan ,  Michael Jason Fronckowiak ,  Xing Chen

IPC: H01L23/00 ,  H01L21/304 ,  H01L21/308 ,  H01L21/311

CPC classification number: H01L23/562 ,  H01L21/304 ,  H01L21/3086 ,  H01L21/31111

Abstract: Exemplary methods of processing a semiconductor substrate may include forming a layer of dielectric material on the semiconductor substrate. The methods may include performing an edge exclusion removal of the layer of dielectric material. The methods may include forming a mask material on the semiconductor substrate. The mask material may contact the dielectric material at an edge region of the semiconductor substrate. The methods may include patterning an opening in the mask material overlying a first surface of the semiconductor substrate. The methods may include etching one or more trenches through the semiconductor substrate.

公开(公告)号：US11769665B2

公开(公告)日：2023-09-26

申请号：US17572963

申请日：2022-01-11

Applicant: Applied Materials, Inc.

Inventor： Amirhasan Nourbakhsh ,  Raman Gaire ,  Tyler Sherwood ,  Lan Yu ,  Roger Quon ,  Siddarth Krishnan

IPC: H01L21/02

CPC classification number: H01L21/02576 ,  H01L21/02532 ,  H01L21/02579

Abstract: Exemplary semiconductor processing methods may include forming a p-type silicon-containing material on a substrate including a first n-type silicon-containing material defining one or more features. The p-type silicon-containing material may extend along at least a portion of the one or more features defined in the first n-type silicon-containing material. The methods may include removing a portion of the p-type silicon-containing material. The portion of the p-type silicon-containing material may be removed from a bottom of the one or more features. The methods may include providing a silicon-containing material. The methods may include depositing a second n-type silicon-containing material on the substrate. The second n-type silicon-containing material may fill the one or more features formed in the first n-type silicon-containing material and may separate regions of remaining p-type silicon-containing material.

公开(公告)号：US20230066610A1

公开(公告)日：2023-03-02

申请号：US17411599

申请日：2021-08-25

Applicant: Applied Materials, Inc.

Inventor： Tyler Sherwood ,  Joseph F. Salfelder ,  Ki Cheol Ahn ,  Kai Ma ,  Raghav Sreenivasan ,  Jason Appell

IPC: H01L23/00

Abstract: Methods of semiconductor processing may include contacting a substrate with a first slurry and a first platen. The substrate may include silicon oxide defining one or more features, a liner extending across the silicon oxide and within the one or more features, and a copper-containing layer deposited on the liner and extending within the one or more features. The first slurry and the first platen may remove a first portion of the copper-containing layer. The methods may include contacting the substrate with a second slurry and a second platen, which may remove at least a portion of the liner. The methods may include contacting the substrate with a third slurry and a third platen, which may remove a second portion of the copper-containing layer. The methods may include contacting the substrate with a fourth slurry and a fourth platen, which may remove at least a portion of the silicon oxide.

公开(公告)号：US11456171B2

公开(公告)日：2022-09-27

申请号：US16953577

申请日：2020-11-20

Applicant: Applied Materials, Inc.

Inventor： Lan Yu ,  Tyler Sherwood

IPC: H01L21/02 ,  H01L29/06 ,  H01L21/762

Abstract: Exemplary methods of forming a semiconductor structure may include forming a liner along sidewalls of a trench defined from a first surface of a semiconductor substrate. The liner may extend along the first surface of the semiconductor substrate. The methods may include filling the trench with a dielectric material. The methods may include removing the dielectric material and the liner from the first surface of the semiconductor substrate. The methods may include forming a layer of the liner across the first surface of the semiconductor substrate and the trench defined within the semiconductor substrate.

公开(公告)号：US20250079356A1

公开(公告)日：2025-03-06

申请号：US18460174

申请日：2023-09-01

Applicant: Applied Materials, Inc.

Inventor： Tyler Sherwood ,  Raghav Sreenivasan

IPC: H01L23/00 ,  H01L21/02 ,  H01L21/67

Abstract: A structure for semiconductor devices having a high-dielectric constant dielectric film on the top surface can be used to form devices that are composed of hybrid bonded structures with reduced dielectric surface area and reduced pitch for metal studs. The dielectric constant of the dielectric film can be about or greater than 8. A device can be formed by hybrid bonding the dielectric film of the structure to a dielectric film of a similar structure. A technique for forming the structure can include selectively depositing the dielectric film via atomic layer deposition after features filled with metal in a top layer of oxide in an oxide-metal-substrate stack. In order to selectively deposit the dielectric film, the metal may be covered with a polymer which can be burned off. A chemical-mechanical polishing technique can be used to precisely form the surface of the structure in preparation for hybrid bonding.