知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

16 条记录 (耗时 0.016 秒)

    CHEMICAL MECHANICAL POLISHING FOR COPPER DISHING CONTROL
    3.
    发明申请
    CHEMICAL MECHANICAL POLISHING FOR COPPER DISHING CONTROL 有权

    公开(公告)号：US20230066610A1

    公开(公告)日：2023-03-02

    申请号：US17411599

    申请日：2021-08-25

    申请人： Applied Materials, Inc.

    发明人： Tyler Sherwood ,  Joseph F. Salfelder ,  Ki Cheol Ahn ,  Kai Ma ,  Raghav Sreenivasan ,  Jason Appell

    IPC分类号： H01L23/00

    摘要： Methods of semiconductor processing may include contacting a substrate with a first slurry and a first platen. The substrate may include silicon oxide defining one or more features, a liner extending across the silicon oxide and within the one or more features, and a copper-containing layer deposited on the liner and extending within the one or more features. The first slurry and the first platen may remove a first portion of the copper-containing layer. The methods may include contacting the substrate with a second slurry and a second platen, which may remove at least a portion of the liner. The methods may include contacting the substrate with a third slurry and a third platen, which may remove a second portion of the copper-containing layer. The methods may include contacting the substrate with a fourth slurry and a fourth platen, which may remove at least a portion of the silicon oxide.

    Method for LCoS DBR multilayer stack protection via sacrificial hardmask for RIE and CMP processes
    6.
    发明授权
    Method for LCoS DBR multilayer stack protection via sacrificial hardmask for RIE and CMP processes 有权

    公开(公告)号：US11573452B2

    公开(公告)日：2023-02-07

    申请号：US17100422

    申请日：2020-11-20

    申请人： Applied Materials, Inc.

    发明人： Lan Yu ,  Benjamin D. Briggs ,  Tyler Sherwood ,  Raghav Sreenivasan

    IPC分类号： G02F1/1335 ,  G02F1/1362

    摘要： Processing methods may be performed to forming a pixel material in a semiconductor structure. The methods may include forming a sacrificial hardmask overlying an uppermost layer of an optical stack of the semiconductor structure, the uppermost layer having a thickness. The methods may include forming a via through the sacrificial hardmask in the optical stack by a first etch process unselective to a metal layer of the semiconductor structure. The methods may include filling the via with a fill material, wherein a portion of the fill material extends over the sacrificial hardmask and contacts the metal layer. The methods may include removing a portion of the fill material external to the via by a removal process selective to the fill material. The methods may also include removing the sacrificial hardmask by a second etch process selective to the sacrificial hardmask while maintaining the thickness of the uppermost layer.

    Methods to fabricate dual pore devices
    7.
    发明授权
    Methods to fabricate dual pore devices 有权

    公开(公告)号：US11536708B2

    公开(公告)日：2022-12-27

    申请号：US16738629

    申请日：2020-01-09

    申请人： Applied Materials, Inc.

    发明人： Mark J. Saly ,  Keenan Navarre Woods ,  Joseph R. Johnson ,  Bhaskar Jyoti Bhuyan ,  William J. Durand ,  Michael Chudzik ,  Raghav Sreenivasan ,  Roger Quon

    IPC分类号： B82Y15/00 ,  B82Y40/00 ,  G01N33/487 ,  B01D67/00 ,  C12Q1/6869

    摘要： Embodiments of the present disclosure provide dual pore sensors and methods for producing these dual pore sensors. The method includes forming a film stack, where the film stack contains two silicon layers and two membrane layers, and then etching the film stack to produce a channel extending therethrough and having two reservoirs and two nanopores. The method also includes depositing a oxide layer on inner surfaces of the reservoirs and nanopores, depositing a dielectric layer on the oxide layer, and forming a metal contact extending through a portion of the stack. The method further includes etching the dielectric layers to form wells, etching the first silicon layer to reveal the protective oxide layer deposited on the inner surfaces of a reservoir, and etching the protective oxide layer deposited on the inner surfaces of the reservoirs and the nanopores.

    STRESS RELAXATION TRENCHES FOR GALLIUM NITRIDE MICROLED LAYERS ON SILICON SUBSTRATES
    10.
    发明公开
    STRESS RELAXATION TRENCHES FOR GALLIUM NITRIDE MICROLED LAYERS ON SILICON SUBSTRATES 审中-公开

    公开(公告)号：US20230369532A1

    公开(公告)日：2023-11-16

    申请号：US17745056

    申请日：2022-05-16

    申请人： Applied Materials, Inc.

    发明人： Tyler Sherwood ,  Raghav Sreenivasan

    IPC分类号： H01L33/00 ,  H01L25/075

    CPC分类号： H01L33/007 ,  H01L25/075 ,  H01L33/32

    摘要： A microLED-quality layer of gallium nitride (GaN) may be formed above a silicon substrate for microLED devices to be formed. Typically, mismatches between the crystal lattice of the GaN and the silicon substrate cause internal stresses that bow the wafer. To relieve these stresses, a pattern of trenches may be etched into the GaN layer between the die or device footprints. These trenches may be etched through the GaN layer, down to the depth of the silicon substrate, or even down into the silicon substrate. Instead of one singular, large wafer with internal stresses, the wafer may thus be divided into multiple small sections with minimal internal stresses. A dielectric gap fill may be applied to fill the trenches, and the resulting wafer may be planarized to expose the surface of the GaN after the gap fill.