公开(公告)号：US20250117561A1

公开(公告)日：2025-04-10

申请号：US18482544

申请日：2023-10-06

Applicant: Applied Materials, Inc.

Inventor： Benjamin D. Briggs

IPC: G06F30/392 ,  G03F7/00 ,  H01L21/48 ,  H01L23/00 ,  H01L23/14 ,  H01L23/538

Abstract: A semiconductor device may include a substrate. The semiconductor device may also include a dielectric material characterized, at least in part, by a dielectric constant. The semiconductor device may include a metallic pathway formed in the dielectric material. The semiconductor device may include a region about the metallic pathway of the semiconductor device may include a plurality of air gaps within the dielectric material and arranged three-dimensionally throughout the region, where the region may include a lower dielectric constant than the dielectric constant of the dielectric material.

公开(公告)号：US11880052B2

公开(公告)日：2024-01-23

申请号：US17100416

申请日：2020-11-20

Applicant: Applied Materials, Inc.

Inventor： Lan Yu ,  Benjamin D. Briggs ,  Tyler Sherwood ,  Raghav Sreenivasan

IPC: G02B5/08 ,  H01L33/46 ,  H01L23/48 ,  H01L33/10 ,  G02F1/1335 ,  G02F1/1362

CPC classification number: G02B5/0808 ,  H01L23/481 ,  H01L33/10 ,  H01L33/46 ,  G02F1/133553 ,  G02F1/136277

Abstract: Processing methods may be performed to form a grounded mirror structure on a semiconductor substrate. The methods may include revealing a metal layer. The metal layer may underlie a spacer layer. The metal layer may be revealed by a dry etch process. The method may include forming a mirror layer overlying the spacer layer and the metal layer. The mirror layer may contact the metal layer. The method may also include forming an oxide inclusion overlying a portion of the mirror layer. The portion of the mirror layer may be external to the spacer layer.

公开(公告)号：US11573452B2

公开(公告)日：2023-02-07

申请号：US17100422

申请日：2020-11-20

Applicant: Applied Materials, Inc.

Inventor： Lan Yu ,  Benjamin D. Briggs ,  Tyler Sherwood ,  Raghav Sreenivasan

IPC: G02F1/1335 ,  G02F1/1362

Abstract: Processing methods may be performed to forming a pixel material in a semiconductor structure. The methods may include forming a sacrificial hardmask overlying an uppermost layer of an optical stack of the semiconductor structure, the uppermost layer having a thickness. The methods may include forming a via through the sacrificial hardmask in the optical stack by a first etch process unselective to a metal layer of the semiconductor structure. The methods may include filling the via with a fill material, wherein a portion of the fill material extends over the sacrificial hardmask and contacts the metal layer. The methods may include removing a portion of the fill material external to the via by a removal process selective to the fill material. The methods may also include removing the sacrificial hardmask by a second etch process selective to the sacrificial hardmask while maintaining the thickness of the uppermost layer.

公开(公告)号：US11908678B2

公开(公告)日：2024-02-20

申请号：US17149399

申请日：2021-01-14

Applicant: Applied Materials, Inc.

Inventor： Lan Yu ,  Benjamin D. Briggs ,  Tyler Sherwood ,  Raghav Sreenivasan ,  Joseph Salfelder

IPC: H01L21/02 ,  H01L21/4757

CPC classification number: H01L21/02024 ,  H01L21/02019 ,  H01L21/47573

Abstract: Processing methods may be performed to form a filled contact hole in a mirror layer of a semiconductor substrate. The method may include forming a contact hole through a mirror layer of the semiconductor substrate by an etch process. The method may include filling the contact hole with a fill material. A portion of the fill material may overlie the mirror layer. The method may also include removing a portion of the fill material external to the contact hole by chemical mechanical polishing landing on the mirror layer.

公开(公告)号：US11586067B2

公开(公告)日：2023-02-21

申请号：US17100407

申请日：2020-11-20

Applicant: Applied Materials, Inc.

Inventor： Lan Yu ,  Benjamin D. Briggs ,  Tyler Sherwood ,  Raghav Sreenivasan

IPC: G02F1/1335 ,  G02F1/1362

Abstract: Processing methods may be performed to form a pixel material in a semiconductor substrate. The methods may include forming a lithographic mask overlying the semiconductor substrate. The lithographic mask may include a window. The method may include forming a via in the semiconductor substrate by a dry etch process through the window. The method may also include forming the pixel material by depositing a fill material in the via.

公开(公告)号：US20220223402A1

公开(公告)日：2022-07-14

申请号：US17149399

申请日：2021-01-14

Applicant: Applied Materials, Inc.

Inventor： Lan Yu ,  Benjamin D. Briggs ,  Tyler Sherwood ,  Raghav Sreenivasan ,  Joseph Salfelder

IPC: H01L21/02 ,  H01L21/4757

Abstract: Processing methods may be performed to form a filled contact hole in a mirror layer of a semiconductor substrate. The method may include forming a contact hole through a mirror layer of the semiconductor substrate by an etch process. The method may include filling the contact hole with a fill material. A portion of the fill material may overlie the mirror layer. The method may also include removing a portion of the fill material external to the contact hole by chemical mechanical polishing landing on the mirror layer.

公开(公告)号：US20220163845A1

公开(公告)日：2022-05-26

申请号：US17100407

申请日：2020-11-20

Applicant: Applied Materials, Inc.

Inventor： Lan Yu ,  Benjamin D. Briggs ,  Tyler Sherwood ,  Raghav Sreenivasan

IPC: G02F1/1335 ,  H01L21/768 ,  G02F1/1362

Abstract: Processing methods may be performed to form a pixel material in a semiconductor substrate. The methods may include forming a lithographic mask overlying the semiconductor substrate. The lithographic mask may include a window. The method may include forming a via in the semiconductor substrate by a dry etch process through the window. The method may also include forming the pixel material by depositing a fill material in the via.

公开(公告)号：US20220163834A1

公开(公告)日：2022-05-26

申请号：US17100400

申请日：2020-11-20

Applicant: Applied Materials, Inc.

Inventor： Lan Yu ,  Benjamin D. Briggs ,  Tyler Sherwood ,  Zihao Yang

IPC: G02F1/1339 ,  H01L21/66

Abstract: Processing methods may be performed to form a pixel isolation structure on a semiconductor substrate. The method may include forming a pixel isolation bilayer on the semiconductor substrate. The pixel isolation bilayer may include a high-k layer overlying a stopping layer. The method may include forming a lithographic mask on a first region of the pixel isolation bilayer. The method may also include etching the pixel isolation bilayer external to the first region. The etching may reveal the semiconductor substrate. The etching may form the pixel isolation structure.

公开(公告)号：US20220163707A1

公开(公告)日：2022-05-26

申请号：US17100416

申请日：2020-11-20

Applicant: Applied Materials, Inc.

Inventor： Lan Yu ,  Benjamin D. Briggs ,  Tyler Sherwood ,  Raghav Sreenivasan

IPC: G02B5/08

Abstract: Processing methods may be performed to form a grounded mirror structure on a semiconductor substrate. The methods may include revealing a metal layer. The metal layer may underlie a spacer layer. The metal layer may be revealed by a dry etch process. The method may include forming a mirror layer overlying the spacer layer and the metal layer. The mirror layer may contact the metal layer. The method may also include forming an oxide inclusion overlying a portion of the mirror layer. The portion of the mirror layer may be external to the spacer layer.

公开(公告)号：US20250046652A1

公开(公告)日：2025-02-06

申请号：US18228846

申请日：2023-08-01

Applicant: Applied Materials, Inc.

Inventor： Benjamin D. Briggs ,  William Charles ,  Gillian Micale

IPC: H01L21/768 ,  H01L23/522

Abstract: A method includes obtaining a base structure including a stack of dielectric layers disposed on a substrate. The stack of dielectric layers includes a first photosensitive dielectric layer including a first photosensitive dielectric material sensitive to a first radiation dose, a second photosensitive dielectric layer including a second photosensitive dielectric material sensitive to a second radiation dose different from the first radiation dose, and a barrier layer disposed between the first photosensitive dielectric layer and the second photosensitive dielectric layer. The method further includes forming a dual damascene structure from the base structure using a dual damascene process.