-
公开(公告)号:US11562909B2
公开(公告)日:2023-01-24
申请号:US16881145
申请日:2020-05-22
发明人: Yu Lei , Xuesong Lu , Tae Hong Ha , Xianmin Tang , Andrew Nguyen , Tza-Jing Gung , Philip A. Kraus , Chung Nang Liu , Hui Sun , Yufei Hu
IPC分类号: H01L21/67 , H01L21/311 , H01L21/02 , H01J37/32 , H01L21/683 , H01L21/3105 , H01L21/8234
摘要: Described is a process to clean up junction interfaces for fabricating semiconductor devices involving forming low-resistance electrical connections between vertically separated regions. An etch can be performed to remove silicon oxide on silicon surface at the bottom of a recessed feature. Described are methods and apparatus for etching up the bottom oxide of a hole or trench while minimizing the effects to the underlying epitaxial layer and to the dielectric layers on the field and the corners of metal gate structures. The method for etching features involves a reaction chamber equipped with a combination of capacitively coupled plasma and inductive coupled plasma. CHxFy gases and plasma are used to form protection layer, which enables the selectively etching of bottom silicon dioxide by NH3—NF3 plasma. Ideally, silicon oxide on EPI is removed to ensure low-resistance electric contact while the epitaxial layer and field/corner dielectric layers are—etched only minimally or not at all.
-
公开(公告)号:US20210366722A1
公开(公告)日:2021-11-25
申请号:US16881145
申请日:2020-05-22
发明人: Yu Lei , Xuesong Lu , Tae Hong Ha , Xianmin Tang , Andrew Nguyen , Tza-Jing Gung , Philip A. Kraus , Chung Nang Liu , Hui Sun , Yufei Hu
IPC分类号: H01L21/311 , H01L21/02 , H01J37/32 , H01L21/683 , H01L21/3105 , H01L21/67 , H01L21/8234
摘要: Described is a process to clean up junction interfaces for fabricating semiconductor devices involving forming low-resistance electrical connections between vertically separated regions. An etch can be performed to remove silicon oxide on silicon surface at the bottom of a recessed feature. Described are methods and apparatus for etching up the bottom oxide of a hole or trench while minimizing the effects to the underlying epitaxial layer and to the dielectric layers on the field and the corners of metal gate structures. The method for etching features involves a reaction chamber equipped with a combination of capacitively coupled plasma and inductive coupled plasma. CHxFy gases and plasma are used to form protection layer, which enables the selectively etching of bottom silicon dioxide by NH3—NF3 plasma. Ideally, silicon oxide on EPI is removed to ensure low-resistance electric contact while the epitaxial layer and field/corner dielectric layers are—etched only minimally or not at all.
-
公开(公告)号:US20220336223A1
公开(公告)日:2022-10-20
申请号:US17846155
申请日:2022-06-22
发明人: Yu Lei , Xuesong Lu , Tae Hong Ha , Xianmin Tang , Andrew Nguyen , Tza-Jing Gung , Philip A. Kraus , Chung Nang Liu , Hui Sun , Yufei Hu
IPC分类号: H01L21/311 , H01L21/02 , H01J37/32 , H01L21/683 , H01L21/3105 , H01L21/67 , H01L21/8234
摘要: Described is a process to clean up junction interfaces for fabricating semiconductor devices involving forming low-resistance electrical connections between vertically separated regions. An etch can be performed to remove silicon oxide on silicon surface at the bottom of a recessed feature. Described are methods and apparatus for etching up the bottom oxide of a hole or trench while minimizing the effects to the underlying epitaxial layer and to the dielectric layers on the field and the corners of metal gate structures. The method for etching features involves a reaction chamber equipped with a combination of capacitively coupled plasma and inductive coupled plasma. CHxFy gases and plasma are used to form protection layer, which enables the selectively etching of bottom silicon dioxide by NH3—NF3 plasma. Ideally, silicon oxide on EPI is removed to ensure low-resistance electric contact while the epitaxial layer and field/corner dielectric layers are—etched only minimally or not at all.
-
-