公开(公告)号：US20170330862A1

公开(公告)日：2017-11-16

申请号：US15662764

申请日：2017-07-28

申请人： Yeong-Hwan CHOE ,  Tae-Joo HWANG ,  Tae-Hong MIN ,  Young-Kun JEE ,  Sang-Uk HAN

发明人： Yeong-Hwan CHOE ,  Tae-Joo HWANG ,  Tae-Hong MIN ,  Young-Kun JEE ,  Sang-Uk HAN

IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L23/48 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/10 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/71 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/06156 ,  H01L2224/10125 ,  H01L2224/131 ,  H01L2224/14156 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75305 ,  H01L2224/81007 ,  H01L2224/81191 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/014

摘要： A semiconductor device includes at least first and second semiconductor chips stacked on each other along a first direction, at least one through-silicon-via (TSV) through at least the first semiconductor chip of the first and second semiconductor chips, a contact pad on the at least one TSV of the first semiconductor chip, the contact pad electrically connecting the TSV of the first semiconductor chip to the second semiconductor chip, and a plurality of dummy pads on the first semiconductor chip, the plurality of dummy pads being spaced apart from each other and from the contact pad along a second direction, and the dummy pads having same heights as the contact pads as measured between respective top and bottom surfaces along the first direction.

公开(公告)号：US10020290B2

公开(公告)日：2018-07-10

申请号：US15662764

申请日：2017-07-28

申请人： Yeong-Hwan Choe ,  Tae-Joo Hwang ,  Tae-Hong Min ,  Young-Kun Jee ,  Sang-Uk Han

发明人： Yeong-Hwan Choe ,  Tae-Joo Hwang ,  Tae-Hong Min ,  Young-Kun Jee ,  Sang-Uk Han

IPC分类号： H01L25/065 ,  H01L23/48 ,  H01L25/00 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/10 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/71 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/06156 ,  H01L2224/10125 ,  H01L2224/131 ,  H01L2224/14156 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75305 ,  H01L2224/81007 ,  H01L2224/81191 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/014

摘要： A semiconductor device includes at least first and second semiconductor chips stacked on each other along a first direction, at least one through-silicon-via (TSV) through at least the first semiconductor chip of the first and second semiconductor chips, a contact pad on the at least one TSV of the first semiconductor chip, the contact pad electrically connecting the TSV of the first semiconductor chip to the second semiconductor chip, and a plurality of dummy pads on the first semiconductor chip, the plurality of dummy pads being spaced apart from each other and from the contact pad along a second direction, and the dummy pads having same heights as the contact pads as measured between respective top and bottom surfaces along the first direction.

公开(公告)号：US20160056101A1

公开(公告)日：2016-02-25

申请号：US14818682

申请日：2015-08-05

申请人： Young-kun JEE ,  Tae-hong MIN ,  Sun-kyoung SEO

发明人： Young-kun JEE ,  Tae-hong MIN ,  Sun-kyoung SEO

IPC分类号： H01L23/498 ,  H01L25/065 ,  H01L23/31

CPC分类号： H01L25/0657 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/3178 ,  H01L23/481 ,  H01L2224/16145 ,  H01L2224/73204 ,  H01L2225/06513

摘要： A chip-stacked semiconductor package including a first chip having a plurality of first real bump pads and a plurality of first dummy bump pads, a second chip on the first chip, the second chip including a plurality of real bumps and a plurality of bridge dummy bumps, the plurality of real bumps electrically connected to the plurality of first real bump pads, the plurality of bridge dummy bumps connected to the plurality of first dummy bump pads, and a sealing member sealing the first chip and the second chip may be provided.

摘要翻译： 一种芯片堆叠半导体封装，包括具有多个第一实际凸块焊盘和多个第一虚拟凸块焊盘的第一芯片，第一芯片上的第二芯片，所述第二芯片包括多个实际凸块和多个桥模 可以提供电连接到多个第一真实凸块焊盘的多个真实凸块，连接到多个第一虚拟凸块焊盘的多个桥接虚拟凸起以及密封第一芯片和第二芯片的密封构件。

公开(公告)号：US08742577B2

公开(公告)日：2014-06-03

申请号：US13550949

申请日：2012-07-17

申请人： Young-kun Jee ,  Sun-kyoung Seo ,  Sang-wook Park ,  Ji-hwan Hwang

发明人： Young-kun Jee ,  Sun-kyoung Seo ,  Sang-wook Park ,  Ji-hwan Hwang

IPC分类号： H01L23/498 ,  H01L23/48

CPC分类号： H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02175 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/05007 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05547 ,  H01L2224/05557 ,  H01L2224/05562 ,  H01L2224/05565 ,  H01L2224/05568 ,  H01L2224/05611 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05686 ,  H01L2224/05687 ,  H01L2224/06181 ,  H01L2224/10145 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16237 ,  H01L2224/16503 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81395 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01327 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1443 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/05042 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor package includes a first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip, and a connection member to electrically connect the first semiconductor chip and the second semiconductor chip. The connection member may include a connection pad disposed on the first semiconductor chip, a connection pillar disposed on the second semiconductor chip, and a bonding member to connect the connection pad and the connection pillar. An anti-contact layer may be formed on at least one surface of the connection pad.

摘要翻译： 半导体封装包括第一半导体芯片，设置在第一半导体芯片上的第二半导体芯片和用于电连接第一半导体芯片和第二半导体芯片的连接构件。 连接构件可以包括设置在第一半导体芯片上的连接焊盘，设置在第二半导体芯片上的连接柱和用于连接连接焊盘和连接柱的接合构件。 可以在连接焊盘的至少一个表面上形成抗接触层。

公开(公告)号：US20080237314A1

公开(公告)日：2008-10-02

申请号：US11907528

申请日：2007-10-12

申请人： Jin Yu ,  Young-Kun Jee ,  Yong-Ho Ko

发明人： Jin Yu ,  Young-Kun Jee ,  Yong-Ho Ko

IPC分类号： B23K31/02 ,  B23K1/00

CPC分类号： B23K1/0016 ,  B23K2101/34 ,  B23K2101/40 ,  B23K2103/18 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13 ,  H01L2224/16503 ,  H01L2224/8181 ,  H01L2924/00014 ,  H05K3/244 ,  H05K3/3463 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： Disclosed is a method of joining electronic package parts, comprising the steps of: reflowing lead-free solders containing alloy elements on top of each of the electronic package parts having a surface treated with copper or nickel; and mounting the surface treated electronic parts on the lead-free solders then reflowing the lead-free solders to generate intermetallic compound between the lead-free solders and the surface treated portion of each of the electronic parts.Alternatively, the method of joining the electronic package parts according to the present invention comprises the steps of: forming a plating layer made of alloy elements on top of each of the electronic parts having a surface treated with copper or nickel and reflowing lead-free solders; and mounting the surface treated electronic parts on the lead-free solders then reflowing the lead-free solders to allow the alloy elements contained in the plating layer to be diffused into the lead-free solders and generate intermetallic compound between the lead-free solders and the surface treated portion of each of the electronic parts.The present invention can prevent brittle fracture of the electronic package parts by deriving alteration of the intermetallic compounds generated from existing lead-free solders when the electronic package parts of electronic devices are solder joined together, thereby ensuring reliability of the electronic devices.

摘要翻译： 公开了一种连接电子封装部件的方法，包括以下步骤：在具有用铜或镍处理的表面的每个电子封装部件的顶部上回流含有合金元素的无铅焊料; 并将表面处理的电子部件安装在无铅焊料上，然后回流无铅焊料，以在无铅焊料和每个电子部件的表面处理部分之间产生金属间化合物。 或者，根据本发明的接合电子封装部件的方法包括以下步骤：在具有用铜或镍处理的表面的每个电子部件的顶部上形成由合金元件制成的镀层和回流无铅焊料 ; 并将表面处理的电子部件安装在无铅焊料上，然后回流无铅焊料，使包含在镀层中的合金元素扩散到无铅焊料中，并在无铅焊料与无铅焊料之间产生金属间化合物 每个电子部件的表面处理部分。 本发明可以通过在电子器件的电子封装部件焊接在一起时导致由现有的无铅焊料产生的金属间化合物的变化来防止电子封装部件的脆性断裂，从而确保电子器件的可靠性。

公开(公告)号：US09543276B2

公开(公告)日：2017-01-10

申请号：US14818682

申请日：2015-08-05

申请人： Young-kun Jee ,  Tae-hong Min ,  Sun-kyoung Seo

发明人： Young-kun Jee ,  Tae-hong Min ,  Sun-kyoung Seo

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40 ,  H01L25/065 ,  H01L23/31 ,  H01L21/56

CPC分类号： H01L25/0657 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/3178 ,  H01L23/481 ,  H01L2224/16145 ,  H01L2224/73204 ,  H01L2225/06513

摘要： A chip-stacked semiconductor package including a first chip having a plurality of first real bump pads and a plurality of first dummy bump pads, a second chip on the first chip, the second chip including a plurality of real bumps and a plurality of bridge dummy bumps, the plurality of real bumps electrically connected to the plurality of first real bump pads, the plurality of bridge dummy bumps connected to the plurality of first dummy bump pads, and a sealing member sealing the first chip and the second chip may be provided.

摘要翻译： 一种芯片堆叠半导体封装，包括具有多个第一实际凸块焊盘和多个第一虚拟凸块焊盘的第一芯片，第一芯片上的第二芯片，所述第二芯片包括多个实际凸块和多个桥模 可以提供电连接到多个第一真实凸块焊盘的多个真实凸块，连接到多个第一虚拟凸块焊盘的多个桥接虚拟凸起以及密封第一芯片和第二芯片的密封构件。

公开(公告)号：US20100240174A1

公开(公告)日：2010-09-23

申请号：US12680760

申请日：2007-12-04

申请人： Jin Yu ,  Young-Kun Jee

发明人： Jin Yu ,  Young-Kun Jee

IPC分类号： H01L21/768 ,  H01L21/50

CPC分类号： H01L21/768 ,  H01L21/76898 ,  H01L24/11 ,  H01L24/12 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/00

摘要： Disclosed are via, a method for formation of via using zinc and zinc alloys, and a process for fabrication of three-dimensional multiple chip stack packages by using the same. In lamination of three-dimensional chips, the chips with reduced defects are rapidly formed by the steps of: punching each of the chips to form a via hole used for a circuit wiring between the chips; depositing a seed layer on an inside of the via hole; forming a plated layer inside the via hole by using Zn and Zn alloys through an electroplating process; removing oxide film from surface of the plated layer; and heat treating the via hole at a temperature of more than melting point of the Zn and Zn alloys. Particularly, the chip having Zn via formed according to the present invention has an advantage of simultaneously overcoming problems in establishment of processing parameters caused by Cu via (e.g., plating mode, current density, influence of additives, pore formation, etc.), problems in successive processes caused by Sn (and other low melting point metals) via (e.g., soldering, chip stack, etc.) and difficulty in mechanical reliability of the process. Additionally, when stacking multiple chips with various functions in the three-dimensional chip stack package, the package can be simply fabricated by controlling contents of constitutional elements in Zn alloy via which has specific thermal properties (such as melting point, thermal expansion coefficient, etc.) suitable for processing temperature of each of the chips.

摘要翻译： 公开了通过使用锌和锌合金形成通孔的方法，以及使用该方法制造三维多芯片堆叠封装的方法。 在三维芯片的层叠中，通过以下步骤快速形成具有减少的缺陷的芯片：冲压每个芯片以形成用于芯片之间的电路布线的通孔; 在所述通孔的内部沉积种子层; 通过使用Zn和Zn合金通过电镀工艺在通孔内形成镀层; 从镀层的表面去除氧化膜; 并在Zn和Zn合金的熔点以上的温度下对通孔进行热处理。 特别地，具有根据本发明形成的Zn通孔的芯片具有同时克服由Cu通孔（例如电镀模式，电流密度，添加剂的影响，孔形成等）引起的加工参数建立中的问题的优点，问题 在由Sn（和其他低熔点金属）经由（例如，焊接，芯片堆叠等）引起的连续工艺中以及该工艺的机械可靠性困难。 此外，当在三维芯片堆叠封装中堆叠具有各种功能的多个芯片时，可以通过控制具有特定热性能（如熔点，热膨胀系数等）的Zn合金中的组成元素的内容物来简单地制造封装 。）适合每个芯片的处理温度。

公开(公告)号：US20130087917A1

公开(公告)日：2013-04-11

申请号：US13550949

申请日：2012-07-17

申请人： Young-kun Jee ,  Sun-kyoung Seo ,  Sang-wook Park ,  Ji-hwan Hwang

发明人： Young-kun Jee ,  Sun-kyoung Seo ,  Sang-wook Park ,  Ji-hwan Hwang

IPC分类号： H01L23/498 ,  H01L23/48

CPC分类号： H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02175 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/05007 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05547 ,  H01L2224/05557 ,  H01L2224/05562 ,  H01L2224/05565 ,  H01L2224/05568 ,  H01L2224/05611 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05686 ,  H01L2224/05687 ,  H01L2224/06181 ,  H01L2224/10145 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16237 ,  H01L2224/16503 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81395 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01327 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1443 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/05042 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor package includes a first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip, and a connection member to electrically connect the first semiconductor chip and the second semiconductor chip. The connection member may include a connection pad disposed on the first semiconductor chip, a connection pillar disposed on the second semiconductor chip, and a bonding member to connect the connection pad and the connection pillar. An anti-contact layer may be formed on at least one surface of the connection pad.

摘要翻译： 半导体封装包括第一半导体芯片，设置在第一半导体芯片上的第二半导体芯片和用于电连接第一半导体芯片和第二半导体芯片的连接构件。 连接构件可以包括设置在第一半导体芯片上的连接焊盘，设置在第二半导体芯片上的连接柱和用于连接连接焊盘和连接柱的接合构件。 可以在连接焊盘的至少一个表面上形成抗接触层。

公开(公告)号：US20120280405A1

公开(公告)日：2012-11-08

申请号：US13462518

申请日：2012-05-02

申请人： Jihwan HWANG ,  Young Kun JEE ,  Jung-Hwan KIM ,  Tae Hong MIN ,  Kwang-chul CHOI

发明人： Jihwan HWANG ,  Young Kun JEE ,  Jung-Hwan KIM ,  Tae Hong MIN ,  Kwang-chul CHOI

IPC分类号： H01L23/48 ,  H01L23/28

CPC分类号： H01L25/50 ,  H01L21/56 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/3185 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/00

摘要： Provided are semiconductor devices and methods of manufacturing the same. The semiconductor package includes a substrate, a first semiconductor chip mounted on the circuit substrate and having a first width, a second semiconductor chip overlying the first semiconductor chip and having a second width greater than the first width, and a first under filler disposed between the first and second semiconductor chips, covering a side surface of the first semiconductor chip and having an inclined side surface.

摘要翻译： 提供半导体器件及其制造方法。 半导体封装包括基板，安装在电路基板上并具有第一宽度的第一半导体芯片，覆盖第一半导体芯片并且具有大于第一宽度的第二宽度的第二半导体芯片，以及设置在第一半导体芯片 第一和第二半导体芯片，覆盖第一半导体芯片的侧表面并具有倾斜的侧表面。

公开(公告)号：US20120223433A1

公开(公告)日：2012-09-06

申请号：US13409480

申请日：2012-03-01

申请人： Young-kun Jee ,  Ji-hwan Hwang ,  Kwang-chul Choi ,  Jung-hwan Kim ,  Tae-hong Min

发明人： Young-kun Jee ,  Ji-hwan Hwang ,  Kwang-chul Choi ,  Jung-hwan Kim ,  Tae-hong Min

IPC分类号： H01L23/488

CPC分类号： B23K35/262 ,  B23K35/3013 ,  B23K35/3033 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/05671 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16503 ,  H01L2224/81097 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01327 ,  H01L2924/15787 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor package including connecting members having a controlled content ratio of gold capable of increasing durability and reliability by preventing an intermetallic compound having high brittleness from being formed. The semiconductor package includes a base substrate; a first semiconductor chip disposed on the base substrate; and a first connecting member for electrically connecting the base substrate and the first semiconductor chip, and comprising a first bonding portion that includes gold and has a first content ratio of gold that is controlled to prevent an intermetallic compound of AuSn4, (Cu, Au)Sn4, or (Ni, Au)Sn4 from being formed.

摘要翻译： 一种半导体封装，其包括通过防止形成具有高脆度的金属间化合物而具有可控含量比的能够提高耐久性和可靠性的连接构件。 半导体封装包括基底; 设置在所述基底基板上的第一半导体芯片; 以及第一连接构件，用于电连接基底基板和第一半导体芯片，并且包括第一接合部分，其包括金并且具有被控制以防止AuSn4（Cu，Au）的金属间化合物的金的第一含量比， Sn4或（Ni，Au）Sn4的形成。