公开(公告)号：US20170278936A1

公开(公告)日：2017-09-28

申请号：US15604646

申请日：2017-05-24

Applicant: Hyun NAMKOONG ,  Dong-Kyum KIM ,  Jung-Hwan KIM ,  Jung Geun JEE ,  Han-Vit YANG ,  Ji-Man YOO

Inventor： Hyun NAMKOONG ,  Dong-Kyum KIM ,  Jung-Hwan KIM ,  Jung Geun JEE ,  Han-Vit YANG ,  Ji-Man YOO

IPC: H01L29/423 ,  H01L27/11519 ,  H01L29/792 ,  H01L27/11582 ,  H01L27/11521 ,  H01L21/28 ,  H01L27/11565 ,  H01L29/66 ,  H01L29/788

CPC classification number: H01L29/42328 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/42324 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7926

Abstract: A semiconductor device includes a substrate, a tunnel insulation pattern on the substrate, a charge storage pattern on the tunnel insulation pattern, a dielectric pattern having a width smaller than a width of the charge storage pattern on the charge storage pattern, a control gate having a width greater than the width of the dielectric pattern on the dielectric pattern, and a metal-containing gate on the control gate.

公开(公告)号：US09698231B2

公开(公告)日：2017-07-04

申请号：US15015116

申请日：2016-02-03

Applicant: Hyun Namkoong ,  Dong-Kyum Kim ,  Jung-Hwan Kim ,  Jung Geun Jee ,  Han-Vit Yang ,  Ji-Man Yoo

Inventor： Hyun Namkoong ,  Dong-Kyum Kim ,  Jung-Hwan Kim ,  Jung Geun Jee ,  Han-Vit Yang ,  Ji-Man Yoo

IPC: H01L29/792 ,  H01L21/336 ,  H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11565 ,  H01L27/11582

CPC classification number: H01L29/42328 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/42324 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7926

Abstract: A semiconductor device includes a substrate, a tunnel insulation pattern on the substrate, a charge storage pattern on the tunnel insulation pattern, a dielectric pattern having a width smaller than a width of the charge storage pattern on the charge storage pattern, a control gate having a width greater than the width of the dielectric pattern on the dielectric pattern, and a metal-containing gate on the control gate.

公开(公告)号：US20150279857A1

公开(公告)日：2015-10-01

申请号：US14539140

申请日：2014-11-12

Applicant: Jung-Hwan KIM ,  Hanvit YANG ,  Jintae NOH ,  Dongchul YOO

Inventor： Jung-Hwan KIM ,  Hanvit YANG ,  Jintae NOH ,  Dongchul YOO

IPC: H01L27/115 ,  H01L23/00

CPC classification number: H01L27/11582

Abstract: Inventive concepts provide semiconductor memory devices and methods of fabricating the same. A stack structure and vertical channel structures are provided on a substrate. The stack structure includes insulating layers and gate electrodes alternately and repeatedly stacked on the substrate. A first vertical channel pattern is disposed in a lower portion of each vertical channel structure. A gate oxide layer is formed on a sidewall of the first vertical channel pattern. A recess region is formed in the substrate between the vertical channel structures. A buffer oxide layer is formed in the recess region. An oxidation inhibiting layer is provided in the substrate to surround the recess region. The oxidation inhibiting layer is in contact with the buffer oxide layer and inhibits growth of the buffer oxide layer.

Abstract translation: 本发明的概念提供半导体存储器件及其制造方法。 堆叠结构和垂直通道结构设置在基板上。 堆叠结构包括在基板上交替重复堆叠的绝缘层和栅电极。 第一垂直通道图案设置在每个垂直通道结构的下部。 栅极氧化层形成在第一垂直沟道图案的侧壁上。 在垂直通道结构之间的衬底中形成凹陷区域。 在凹陷区域中形成缓冲氧化物层。 在基板中设置氧化抑制层以包围凹部。 氧化抑制层与缓冲氧化物层接触并抑制缓冲氧化物层的生长。

公开(公告)号：US20150130078A1

公开(公告)日：2015-05-14

申请号：US14499591

申请日：2014-09-29

Applicant: Ji-seok Hong ,  Won-keun Kim ,  Tae-je Cho ,  Jung-hwan Kim

Inventor： Ji-seok Hong ,  Won-keun Kim ,  Tae-je Cho ,  Jung-hwan Kim

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/34 ,  H01L23/48

CPC classification number: H01L23/34 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3157 ,  H01L23/367 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L25/105 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1076 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package of a POP structure includes first and second semiconductor packages, the second directly mounted on the first and containing a plurality of semiconductor chips. Chips in the second package are electrically connected via a through-electrode and the first and second packages are connected through a connection member disposed on the top surface of the first package.

Abstract translation: POP结构的半导体封装包括第一和第二半导体封装，第二半导体封装直接安装在第一和第二半导体封装上，并且包含多个半导体芯片。 第二封装中的芯片经由贯通电极电连接，第一和第二封装通过布置在第一封装的顶表面上的连接构件连接。

公开(公告)号：US08975867B2

公开(公告)日：2015-03-10

申请号：US13123250

申请日：2009-10-13

Applicant: Heegyu Kim ,  Seogjin Yoon ,  Jung-Hwan Kim

Inventor： Heegyu Kim ,  Seogjin Yoon ,  Jung-Hwan Kim

IPC: H02J7/00 ,  H02J7/14 ,  H01M10/42 ,  H01M2/02 ,  H01M2/30 ,  H01M10/052

CPC classification number: H01M10/425 ,  H01M2/0207 ,  H01M2/021 ,  H01M2/30 ,  H01M10/052 ,  H01M2200/106

Abstract: Disclosed herein is a secondary battery pack including a battery cell having a pair of coupling grooves, each of the coupling grooves having a predetermined depth, an insulative mounting member mounted to the top of the battery cell, a protection circuit module (PCM) having a pair of connection coupling members protruding downward, and an insulative cap coupled to the top of the battery cell, wherein the connection coupling members are inserted into coupling grooves formed at electrode terminals of the battery cell through openings of the insulative mounting member in a state in which the insulative mounting member is mounted to the top of the battery cell, thereby achieving the coupling of the PCM to the battery cell and the insulative mounting member and the electrical connection between the battery cell and the PCM.

Abstract translation: 本发明公开了一种二次电池组，包括具有一对耦合槽的电池单元，每个耦合槽具有预定深度，安装在电池单元顶部的绝缘安装构件，具有 一对连接联接构件向下突出，以及连接到电池单元的顶部的绝缘帽，其中连接联接构件通过绝缘安装构件的开口插入形成在电池单元的电极端子处的联接槽中， 绝缘安装构件被安装到电池单元的顶部，从而实现PCM与电池单元和绝缘安装构件的耦合以及电池单元和PCM之间的电连接。

公开(公告)号：US20140300004A1

公开(公告)日：2014-10-09

申请号：US14294052

申请日：2014-06-02

Applicant: Eun-Kyoung CHOI ,  SeYoung JEONG ,  Kwang-chul CHOI ,  Tae Hong MIN ,  Chungsun LEE ,  Jung-Hwan KIM

Inventor： Eun-Kyoung CHOI ,  SeYoung JEONG ,  Kwang-chul CHOI ,  Tae Hong MIN ,  Chungsun LEE ,  Jung-Hwan KIM

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/522

CPC classification number: H01L24/97 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3672 ,  H01L23/3677 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Provided are a semiconductor package and a method of fabricating the same. In one embodiment, to fabricate a semiconductor package, a wafer having semiconductor chips fabricated therein is provided. A heat sink layer is formed over the wafer. The heat sink layer contacts top surfaces of the semiconductor chips. Thereafter, the plurality of semiconductor chips are singulated from the wafer.

Abstract translation: 提供半导体封装及其制造方法。 在一个实施例中，为了制造半导体封装，提供其中制造有半导体芯片的晶片。 在晶片上形成散热层。 散热层接触半导体芯片的顶表面。 此后，从晶片上分离多个半导体芯片。

公开(公告)号：US08852766B2

公开(公告)日：2014-10-07

申请号：US13122302

申请日：2009-10-13

Applicant: Seogjin Yoon ,  Ki Eob Moon ,  Jung-Hwan Kim

Inventor： Seogjin Yoon ,  Ki Eob Moon ,  Jung-Hwan Kim

IPC: H01M10/42 ,  H01M2/04 ,  H01M2/10 ,  H01M10/052

CPC classification number: H01M2/0404 ,  H01M2/0473 ,  H01M2/1061 ,  H01M10/052 ,  H01M10/425 ,  H01M2200/103 ,  H01M2200/106

Abstract: Disclosed herein is a secondary battery pack including a battery cell having an electrode assembly of a cathode/separator/anode structure mounted in a battery case together with an electrolyte in a sealed state, an insulative mounting member having openings, through which electrode terminals of the battery cell are exposed to the outside, the insulative mounting member being configured to have a structure in which a safety element is mounted to the top of the insulative mounting member, the insulative mounting member being disposed in direct contact with the top of the battery cell, and an insulative cap coupled to the top of the battery cell so that the insulative cap surrounds the insulative mounting member in a state in which the safety element is mounted to the insulative mounting member, wherein the battery case is provided at the top thereof with a coupling groove, and the insulative cap is provided at the bottom thereof with a coupling protrusion formed in a shape corresponding to the coupling groove, the coupling of the insulative cap to the battery cell being achieved by the insertion of the coupling protrusion into the coupling groove.

Abstract translation: 本文公开了一种二次电池组，其包括具有阴极/隔板/阳极结构的电极组件的电池组，阴极/隔板/阳极结构与密封状态的电解质一起安装在电池壳体中，具有开口的绝缘安装构件， 电池单元暴露于外部，绝缘安装构件被构造成具有将安全元件安装到绝缘安装构件的顶部的结构，绝缘安装构件设置成与电池单元的顶部直接接触 以及耦合到电池单元的顶部的绝缘帽，使得绝缘帽在安全元件安装到绝缘安装构件的状态下围绕绝缘安装构件，其中电池壳体在其顶部设置有 耦合槽，并且绝缘帽在其底部设置有形成为相应形状的联接突起 通过将耦合突起插入耦合槽来实现绝缘帽与电池单元的耦合。

公开(公告)号：US20140213039A1

公开(公告)日：2014-07-31

申请号：US14150906

申请日：2014-01-09

Applicant: Chungsun LEE ,  Jung-Hwan KIM ,  Kwang-chul CHOI ,  Un-Byoung KANG ,  Jeon Il LEE

Inventor： Chungsun LEE ,  Jung-Hwan KIM ,  Kwang-chul CHOI ,  Un-Byoung KANG ,  Jeon Il LEE

IPC: H01L21/683 ,  H01L21/302

CPC classification number: H01L21/302 ,  H01L21/02057 ,  H01L21/6835 ,  H01L21/6836 ,  H01L24/03 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/92 ,  H01L2224/9222 ,  H01L2224/92222 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/15311 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2221/68304 ,  H01L21/304 ,  H01L2221/68368 ,  H01L21/78 ,  H01L2224/81

Abstract: Methods processing substrates are provided. The method may include providing a bonding layer between a substrate and a carrier to bond the substrate to the carrier, processing the substrate while the substrate is supported by the carrier, and removing the bonding layer to separate the substrate from the carrier. The bonding layer may include a thermosetting glue layer and thermosetting release layers provided on opposing sides of the thermosetting glue layer.

Abstract translation: 提供了处理衬底的方法。 该方法可以包括在衬底和载体之间提供结合层，以将衬底粘合到载体上，在衬底被载体支撑的同时处理衬底，以及去除结合层以使衬底与载体分离。 接合层可以包括热固性胶层和设置在热固性胶层的相对侧上的热固性剥离层。

公开(公告)号：US08677245B2

公开(公告)日：2014-03-18

申请号：US12715489

申请日：2010-03-02

Applicant: Mee Sun Song ,  Jung Hwan Kim ,  Won-Kyu Lee

Inventor： Mee Sun Song ,  Jung Hwan Kim ,  Won-Kyu Lee

IPC: G06F3/00

CPC classification number: G06F17/30554 ,  G06F3/0483 ,  G06F3/0488

Abstract: Provided are an apparatus and method of grouping and displaying messages. The apparatus verifies a grouping condition corresponding to messages, generates group message boxes obtained by grouping the messages based on the grouping condition, and displays the group message boxes. The group message boxes are connected with a reference axis, and the reference axis is used to arrange the group message boxes according to the grouping condition.

Abstract translation: 提供了分组和显示消息的装置和方法。 设备验证与消息相对应的分组条件，生成基于分组条件对消息进行分组而获得的组消息框，并显示组消息框。 组消息框与参考轴相连，参考轴用于根据分组条件排列组消息框。

公开(公告)号：US20140061757A1

公开(公告)日：2014-03-06

申请号：US13971279

申请日：2013-08-20

Applicant: SUNGGIL KIM ,  Sunghoi Hur ,  Jung-Hwan Kim ,  HongSuk Kim ,  Guk-Hyon Yon ,  JaeHo Choi

Inventor： SUNGGIL KIM ,  Sunghoi Hur ,  Jung-Hwan Kim ,  HongSuk Kim ,  Guk-Hyon Yon ,  JaeHo Choi

IPC: H01L29/788 ,  H01L29/66

CPC classification number: H01L29/788 ,  H01L21/764 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11582 ,  H01L29/42332 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833

Abstract: A semiconductor device includes a semiconductor substrate having a plurality of active regions defined by a trench. A gate electrode crosses the plurality of active regions. A plurality of charge storing cells is disposed between the gate electrode and each of the plurality of active regions. A porous insulating layer is disposed between the gate electrode and the plurality of charge storing cells. The porous insulating layer includes a portion extended over the trench. An air gap is disposed between the extended portion of the porous insulating layer and a bottom surface of the trench.

Abstract translation: 半导体器件包括具有由沟槽限定的多个有源区的半导体衬底。 栅电极与多个有源区交叉。 多个电荷存储单元设置在栅电极和多个有源区域中的每一个之间。 多孔绝缘层设置在栅电极和多个电荷存储单元之间。 多孔绝缘层包括在沟槽上延伸的部分。 空隙设置在多孔绝缘层的延伸部分和沟槽的底表面之间。