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    Method of controlled low-k via etch for Cu interconnections
    2.
    发明授权
    Method of controlled low-k via etch for Cu interconnections 有权
    用于Cu互连的受控低k通孔蚀刻的方法

    公开(公告)号：US07906426B2

    公开(公告)日：2011-03-15

    申请号：US11788969

    申请日：2007-04-23

    Applicant: Wuping Liu ,  Johnny Widodo ,  Teck Jung Tang ,  Jing Hui Li ,  Han Wah Ng ,  Larry A. Clevenger ,  Hermann Wendt

    Inventor： Wuping Liu ,  Johnny Widodo ,  Teck Jung Tang ,  Jing Hui Li ,  Han Wah Ng ,  Larry A. Clevenger ,  Hermann Wendt

    IPC: H01L21/4763

    CPC classification number: H01L21/76802 ,  H01L21/02063 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31138

    Abstract: An interconnect stack and a method of manufacturing the same wherein the interconnect has vertical sidewall vias. The interconnect stack includes a substrate, a metal interconnect formed in the substrate, an etch stop formed on the substrate and the metal interconnect, and an interlayer dielectric (ILD) layer having at least one via formed therein extending through a transition layer formed on the etch stop layer. The via is formed by etching the ILD to a first depth and ashing the interconnect stack to modify a portion of the ILD between the portion of the via formed by etching and the transition layer. Ashing converts this portion of the ILD to an oxide material. The method includes wet etching the interconnect to remove the oxide material and a portion of the transition layer to form a via extending through the ILD to the etch stop layer.

    Abstract translation: 互连堆叠及其制造方法，其中互连具有垂直侧壁通孔。 互连堆叠包括衬底，形成在衬底中的金属互连，形成在衬底上的蚀刻阻挡层和金属互连，以及层间电介质（ILD）层，其具有形成在其中的至少一个通孔，其延伸穿过形成在衬底上的过渡层 蚀刻停止层。 通过将ILD蚀刻到第一深度并且使互连堆叠灰化以修改通过蚀刻形成的通路的部分与过渡层之间的ILD的一部分而形成通孔。 灰化将ILD的这部分转化为氧化物材料。 该方法包括湿蚀刻互连以去除氧化物材料和过渡层的一部分，以形成延伸穿过ILD到蚀刻停止层的通孔。

    Integrated circuit hard mask processing system
    4.
    发明授权
    Integrated circuit hard mask processing system 有权
    集成电路硬掩模处理系统

    公开(公告)号：US08018061B2

    公开(公告)日：2011-09-13

    申请号：US12567490

    申请日：2009-09-25

    Applicant: Wuping Liu ,  Michael Beck ,  John A. Fitzsimmons

    Inventor： Wuping Liu ,  Michael Beck ,  John A. Fitzsimmons

    IPC: H01L21/31

    CPC classification number: H01L21/76804 ,  H01L21/02063 ,  H01L21/76814 ,  H01L21/76835

    Abstract: An integrated circuit processing system is provided including a substrate having an integrated circuit; an interconnect layer over the integrated circuit; a low-K dielectric layer over the interconnect layer; a hard mask layer over the low-K dielectric layer; a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; and an interconnect metal in the via opening.

    Abstract translation: 提供一种集成电路处理系统，其包括具有集成电路的基板; 集成电路上的互连层; 互连层上的低K电介质层; 在低K电介质层上的硬掩模层; 穿过所述硬掩模层和所述低K电介质层到所述互连层的通孔; 和通孔开口中的互连金属。

    Protruded contact and insertion of inter-layer-dielectric material to match damascene hardmask to improve undercut for low-k interconnects
    7.
    发明申请
    Protruded contact and insertion of inter-layer-dielectric material to match damascene hardmask to improve undercut for low-k interconnects 有权
    突出接触和插入层间介电材料以匹配镶嵌硬掩模，以改善低k互连的底切

    公开(公告)号：US20070264820A1

    公开(公告)日：2007-11-15

    申请号：US11434318

    申请日：2006-05-15

    Applicant: Wuping Liu ,  Raymond Joy ,  Beichao Zhang ,  Liang Hsia ,  Boon Seah ,  Shyam Pal

    Inventor： Wuping Liu ,  Raymond Joy ,  Beichao Zhang ,  Liang Hsia ,  Boon Seah ,  Shyam Pal

    IPC: H01L21/4763

    CPC classification number: H01L21/76802 ,  H01L21/02063 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76814

    Abstract: An embodiment of the invention shows a process to form a damascene opening preferably without hardmask overhang or dielectric layer undercut/void. The low-k dielectric material can be sandwiched in two hardmask films to form the dielectric film through which an interconnect opening is etched. A first example embodiment comprises the following. We form a lower interconnect and an insulating layer over a semiconductor structure. We form a first hardmask a dielectric layer, and a second hardmask layer, over the lower interconnect and insulating layer. We etch a first interconnect opening in the first hardmask, the dielectric layer and the second hardmask layer. Lastly, we form an interconnect in the first interconnect opening.

    Abstract translation: 本发明的一个实施例示出了一种形成镶嵌开口的方法，优选地不具有硬掩模悬垂或电介质层底切/空隙。 低k电介质材料可以被夹在两个硬掩模膜中以形成蚀刻互连开口的电介质膜。 第一示例性实施例包括以下。 我们在半导体结构上形成下互连和绝缘层。 我们在下互连和绝缘层上形成第一硬掩模介电层和第二硬掩模层。 我们蚀刻第一硬掩模，电介质层和第二硬掩模层中的第一互连开口。 最后，我们在第一个互连开口中形成互连。

    Method of fabricating semiconductor devices including PMOS devices having embedded SiGe
    10.
    发明授权
    Method of fabricating semiconductor devices including PMOS devices having embedded SiGe 有权
    制造包括具有嵌入SiGe的PMOS器件的半导体器件的方法

    公开(公告)号：US09449834B2

    公开(公告)日：2016-09-20

    申请号：US13289983

    申请日：2011-11-04

    Applicant: Qingsong Wei ,  Wei Lu ,  Wuping Liu ,  Yonggen He

    Inventor： Qingsong Wei ,  Wei Lu ,  Wuping Liu ,  Yonggen He

    IPC: H01L21/3205 ,  H01L21/306 ,  H01L21/265 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L21/308

    CPC classification number: H01L21/30608 ,  H01L21/26533 ,  H01L21/3083 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

    Abstract: A method of fabricating semiconductor device is provided. First, a recess having a substantially rectangular cross section is formed in a substrate. Then, oxide layers are formed on sidewalls and bottom of the recess by oxygen ion implantation process, wherein oxide layer on sidewalls of recess is thinner than oxide layer on bottom of recess. Thereafter, oxide layer on sidewalls of recess is completely removed, and only a portion of oxide layer on bottom of recess remains. Then, sidewalls of recess are shaped into Σ form by orientation selective wet etching using oxide layer remained on bottom of recess as a stop layer. Finally, oxide layer on bottom of recess is removed. By forming oxide layer on bottom of recess and using it as stop layer in subsequent orientation selective wet etching, the disclosed method can prevent a Σ-shaped recess with a cuspate bottom.

    Abstract translation: 提供一种制造半导体器件的方法。 首先，在基板上形成具有大致矩形截面的凹部。 然后，通过氧离子注入工艺在凹槽的侧壁和底部形成氧化物层，其中凹陷侧壁上的氧化物层比凹部底部的氧化物层薄。 此后，凹槽侧壁上的氧化物层被完全去除，并且凹部底部仅有一部分氧化物层残留。 然后，通过使用保留在凹部底部的氧化物层作为停止层的取向选择性湿蚀刻将凹部的侧壁成形为Σ形式。 最后，去除凹槽底部的氧化物层。 通过在凹部的底部形成氧化物层并将其用作随后的取向选择性湿蚀刻中的停止层，所公开的方法可以防止具有尖端底部的Σ形凹部。

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