Integrated circuit manufacturing method using hard mask
    1.
    发明授权
    Integrated circuit manufacturing method using hard mask 有权
    使用硬掩模的集成电路制造方法

    公开(公告)号:US07615484B2

    公开(公告)日:2009-11-10

    申请号:US11739595

    申请日:2007-04-24

    Abstract: An integrated circuit hard mask processing system is provided including providing a substrate having an integrated circuit; forming an interconnect layer over the integrated circuit; applying a low-K dielectric layer over the interconnect layer; applying a hard mask layer over the low-K dielectric layer; forming a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; applying a first fluid and a second fluid in the via opening for removing an overhang of the hard mask layer; depositing an interconnect metal in the via opening; and chemical-mechanical polishing the interconnect metal and the ultra low-K dielectric layer.

    Abstract translation: 提供一种集成电路硬掩模处理系统,包括提供具有集成电路的基板; 在所述集成电路上形成互连层; 在所述互连层上施加低K电介质层; 在低K电介质层上施加硬掩模层; 通过所述硬掩模层和所述低K电介质层形成通孔至所述互连层; 在所述通孔开口中施加第一流体和第二流体以去除所述硬掩模层的突出端; 在所述通孔开口中沉积互连金属; 并对互连金属和超低K电介质层进行化学机械抛光。

    Integrated circuit hard mask processing system
    2.
    发明授权
    Integrated circuit hard mask processing system 有权
    集成电路硬掩模处理系统

    公开(公告)号:US08018061B2

    公开(公告)日:2011-09-13

    申请号:US12567490

    申请日:2009-09-25

    Abstract: An integrated circuit processing system is provided including a substrate having an integrated circuit; an interconnect layer over the integrated circuit; a low-K dielectric layer over the interconnect layer; a hard mask layer over the low-K dielectric layer; a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; and an interconnect metal in the via opening.

    Abstract translation: 提供一种集成电路处理系统,其包括具有集成电路的基板; 集成电路上的互连层; 互连层上的低K电介质层; 在低K电介质层上的硬掩模层; 穿过所述硬掩模层和所述低K电介质层到所述互连层的通孔; 和通孔开口中的互连金属。

    INTEGRATED CIRCUIT HARD MASK PROCESSING SYSTEM
    3.
    发明申请
    INTEGRATED CIRCUIT HARD MASK PROCESSING SYSTEM 有权
    集成电路硬掩模处理系统

    公开(公告)号:US20100013104A1

    公开(公告)日:2010-01-21

    申请号:US12567490

    申请日:2009-09-25

    Abstract: An integrated circuit processing system is provided including a substrate having an integrated circuit; an interconnect layer over the integrated circuit; a low-K dielectric layer over the interconnect layer; a hard mask layer over the low-K dielectric layer; a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; and an interconnect metal in the via opening.

    Abstract translation: 提供一种集成电路处理系统,其包括具有集成电路的基板; 集成电路上的互连层; 互连层上的低K电介质层; 在低K电介质层上的硬掩模层; 穿过所述硬掩模层和所述低K电介质层到所述互连层的通孔; 和通孔开口中的互连金属。

    INTEGRATED CIRCUIT HARD MASK PROCESSING SYSTEM
    4.
    发明申请
    INTEGRATED CIRCUIT HARD MASK PROCESSING SYSTEM 有权
    集成电路硬掩模处理系统

    公开(公告)号:US20080265409A1

    公开(公告)日:2008-10-30

    申请号:US11739595

    申请日:2007-04-24

    Abstract: An integrated circuit hard mask processing system is provided including providing a substrate having an integrated circuit; forming an interconnect layer over the integrated circuit; applying a low-K dielectric layer over the interconnect layer; applying a hard mask layer over the low-K dielectric layer; forming a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; applying a first fluid and a second fluid in the via opening for removing an overhang of the hard mask layer; depositing an interconnect metal in the via opening; and chemical-mechanical polishing the interconnect metal and the ultra low-K dielectric layer.

    Abstract translation: 提供一种集成电路硬掩模处理系统,包括提供具有集成电路的基板; 在所述集成电路上形成互连层; 在所述互连层上施加低K电介质层; 在低K电介质层上施加硬掩模层; 通过所述硬掩模层和所述低K电介质层形成通孔至所述互连层; 在所述通孔开口中施加第一流体和第二流体以去除所述硬掩模层的突出端; 在所述通孔开口中沉积互连金属; 并对互连金属和超低K电介质层进行化学机械抛光。

    OXIDANT AND PASSIVANT COMPOSITION AND METHOD FOR USE IN TREATING A MICROELECTRONIC STRUCTURE
    5.
    发明申请
    OXIDANT AND PASSIVANT COMPOSITION AND METHOD FOR USE IN TREATING A MICROELECTRONIC STRUCTURE 失效
    氧化剂和有害成分及其在微电子结构处理中的应用

    公开(公告)号:US20090008361A1

    公开(公告)日:2009-01-08

    申请号:US11774041

    申请日:2007-07-06

    CPC classification number: C23G1/103 H01L21/02063

    Abstract: A composition that may be used for cleaning a metal containing conductor layer, such as a copper containing conductor layer, within a microelectronic structure includes an aqueous acid, along with an oxidant material and a passivant material contained within the aqueous acid. The composition does not include an abrasive material. The composition is particularly useful for cleaning a residue from a copper containing conductor layer and an adjoining dielectric layer that provides an aperture for accessing the copper containing conductor layer within a microelectronic structure.

    Abstract translation: 微电子结构中可用于清洗含金属导体层(例如含铜导电体层)的组合物包括酸水溶液以及氧化剂材料和含水酸性物质中的钝化材料。 组合物不包括研磨材料。 所述组合物特别可用于从含铜导体层和邻接的介电层清洁残留物,所述相邻介电层提供用于在微电子结构内进入含铜导体层的孔。

    Minimizing low-k dielectric damage during plasma processing
    6.
    发明授权
    Minimizing low-k dielectric damage during plasma processing 有权
    最小化等离子体处理过程中的低k电介质损伤

    公开(公告)号:US07691736B2

    公开(公告)日:2010-04-06

    申请号:US11352047

    申请日:2006-02-10

    Abstract: Embodiments of the invention provide a semiconductor device having dielectric material and its method of manufacture. A method comprises a short (≦2 sec) flash activation of an ILD surface followed by flowing a precursor such as silane, DEMS, over the activated ILD surface. The precursor reacts with the activated ILD surface thereby selectively protecting the ILD surface. The protected ILD surface is resistant to plasma processing damage. The protected ILD surface eliminates the requirement of using a hard mask to protect a dielectric from plasma damage.

    Abstract translation: 本发明的实施例提供一种具有介电材料的半导体器件及其制造方法。 一种方法包括ILD表面的短(≦̸ 2秒)闪光激活,随后在活化的ILD表面上流动诸如硅烷DEMS之类的前体。 前体与活化的ILD表面反应,从而有选择地保护ILD表面。 受保护的ILD表面耐等离子体处理损伤。 受保护的ILD表面消除了使用硬掩模来保护电介质免受等离子体损伤的要求。

    Oxidant and passivant composition and method for use in treating a microelectronic structure
    7.
    发明授权
    Oxidant and passivant composition and method for use in treating a microelectronic structure 失效
    氧化剂和钝化剂组合物和用于处理微电子结构的方法

    公开(公告)号:US07670497B2

    公开(公告)日:2010-03-02

    申请号:US11774041

    申请日:2007-07-06

    CPC classification number: C23G1/103 H01L21/02063

    Abstract: A composition that may be used for cleaning a metal containing conductor layer, such as a copper containing conductor layer, within a microelectronic structure includes an aqueous acid, along with an oxidant material and a passivant material contained within the aqueous acid. The composition does not include an abrasive material. The composition is particularly useful for cleaning a residue from a copper containing conductor layer and an adjoining dielectric layer that provides an aperture for accessing the copper containing conductor layer within a microelectronic structure.

    Abstract translation: 微电子结构中可用于清洗含金属导体层(例如含铜导电体层)的组合物包括酸水溶液以及氧化剂材料和含水酸性物质中的钝化材料。 组合物不包括研磨材料。 所述组合物特别可用于从含铜导体层和邻接的介电层清洁残留物,所述相邻介电层提供用于在微电子结构内进入含铜导体层的孔。

    RIGHTS MANAGEMENT OF CONTENT
    8.
    发明申请

    公开(公告)号:US20190238319A1

    公开(公告)日:2019-08-01

    申请号:US16262528

    申请日:2019-01-30

    Applicant: Michael Beck

    Inventor: Michael Beck

    Abstract: Data characterizing a secure rights managed container can be received. The secure rights managed container can include a first content holder. The first content holder can include a first content, first terms and conditions, and a symmetric key. The first content can be encrypted by the symmetric key and configured to enable a modification of a blockchain. The first terms and conditions can specify access to the first content, and the symmetric key can be encrypted by a public key of a clearing server. A first context of a recipient and a first credential of the recipient can be received. The clearing server can determine access to the first content by the recipient at least by comparing the first terms and conditions to the first context and the first credential. The first content can be provided to the recipient for executing the modification of the blockchain.

    Method and apparatus for automatically wrapping utensils in a napkin
    9.
    发明申请
    Method and apparatus for automatically wrapping utensils in a napkin 审中-公开
    用于将餐具自动包裹在餐巾中的方法和装置

    公开(公告)号:US20150321775A1

    公开(公告)日:2015-11-12

    申请号:US14271724

    申请日:2014-05-07

    Applicant: Michael Beck

    Inventor: Michael Beck

    Abstract: An apparatus and method for automatically rolling a napkin around a set of dining utensils, wherein the apparatus can repeat the method quickly to individually wrap a plurality of sets of utensils in napkins. The apparatus comprises a housing for a first transfer unit for receiving a set of unwrapped utensil and a napkin and configured to automatically deliver the unwrapped utensils and napkin to a platform for wrapping. A lift plate holds a plurality of napkins and delivers a single napkin to unwrapped silverware. A rolling assembly rotatable around the unwrapped utensils and the napkin is configured to hold the utensils and to roll the napkin around the unwrapped utensils and to deliver the wrapped utensils to a second transfer unit configured to provide the wrapped utensils to a bin for storage.

    Abstract translation: 一种用于自动地将卫生巾卷绕在一组餐具周围的装置和方法,其中该装置可以快速重复该方法以将多组餐具单独地包裹在餐巾中。 该装置包括用于第一传送单元的壳体,用于接收一组展开的餐具和卫生巾,并且被配置为自动地将展开的餐具和餐巾递送到用于包装的平台。 升降板保持多个餐巾,并将单个卫生巾递送到展开的银器。 围绕未展开的餐具和卫生巾旋转的滚动组件被配置为保持餐具并将餐巾卷绕在展开的餐具周围并将包裹的餐具输送到第二转印单元,该第二转印单元被配置为将包裹的餐具提供到用于储存的箱子中。

    Methods of Manufacturing Semiconductor Devices and Structures Thereof
    10.
    发明申请
    Methods of Manufacturing Semiconductor Devices and Structures Thereof 有权
    制造半导体器件及其结构的方法

    公开(公告)号:US20120074536A1

    公开(公告)日:2012-03-29

    申请号:US13310923

    申请日:2011-12-05

    CPC classification number: H01L21/76808 H01L21/76832

    Abstract: Methods of manufacturing semiconductor devices are disclosed. A preferred embodiment comprises a method of manufacturing a semiconductor device, the method including providing a workpiece, disposing an etch stop layer over the workpiece, and disposing a material layer over the etch stop layer. The material layer includes a transition layer. The method includes patterning the material layer partially with a first pattern, and patterning the material layer partially with a second pattern. Patterning the material layer partially with the second pattern further comprises simultaneously completely patterning the material layer with the first pattern.

    Abstract translation: 公开了制造半导体器件的方法。 优选实施例包括制造半导体器件的方法,该方法包括提供工件,在工件上设置蚀刻停止层,以及在蚀刻停止层上设置材料层。 材料层包括过渡层。 该方法包括以第一图案部分地图案化材料层,并以第二图案部分地图案化材料层。 用第二图案部分地对材料层进行图案化还包括用第一图案同时完全图案化材料层。

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