公开(公告)号：US08102054B2

公开(公告)日：2012-01-24

申请号：US12860946

申请日：2010-08-23

Applicant: Bei Chao Zhang ,  Chim Seng Seet ,  Juan Boon Tan ,  Fan Zhang ,  Yong Chiang Ee ,  Bo Tao ,  Tong Qing Chen ,  Liang Choo Hsia

Inventor： Bei Chao Zhang ,  Chim Seng Seet ,  Juan Boon Tan ,  Fan Zhang ,  Yong Chiang Ee ,  Bo Tao ,  Tong Qing Chen ,  Liang Choo Hsia

IPC: H01L23/48 ,  H01L23/50 ,  H01L29/40

CPC classification number: H01L23/5329 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with a dielectric layer formed thereon. The dielectric layer having a conductive line disposed in an upper portion of the dielectric layer. The substrate is processed to produce a top surface of the dielectric layer that is not coplanar with a top surface of the conductive line to form a stepped topography.

Abstract translation: 提出了一种形成半导体器件的方法。 该方法包括提供用其上形成的电介质层制备的衬底。 电介质层具有布置在电介质层上部的导线。 处理衬底以产生与导电线的顶表面不共面的电介质层的顶表面，以形成阶梯形状。

公开(公告)号：US20090250818A1

公开(公告)日：2009-10-08

申请号：US12486521

申请日：2009-06-17

Applicant: Bei Chao Zhang ,  Chun Hui Low ,  Hong Lim Lee ,  Sang Yee Loong ,  Qiang Guo

Inventor： Bei Chao Zhang ,  Chun Hui Low ,  Hong Lim Lee ,  Sang Yee Loong ,  Qiang Guo

IPC: H01L23/522

CPC classification number: H01L21/76802 ,  H01L21/76805 ,  H01L21/76814

Abstract: An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.

Abstract translation: 描述了一种用于提高半导体器件中的电迁移阻力的集成方法。 在包括上电介质层，中间TiN ARC和下第一金属层的堆叠中形成通孔，并且填充有共形扩散阻挡层和第二金属层。 一个关键特征是可以选择蚀刻工艺来改变通孔底部的形状和位置。 在第一金属层中形成圆形或部分圆形的底部，以减小扩散阻挡层附近的机械应力。 另一方面，当第一金属层暴露于后续处理步骤时，选择在TiN ARC上或其中停止的平底，这是首要考虑的问题。 发现耐电迁移性低于在第一金属层中形成的平坦底部的通孔结构。

公开(公告)号：US07524755B2

公开(公告)日：2009-04-28

申请号：US11358934

申请日：2006-02-22

Applicant: Johnny Widodo ,  Bei Chao Zhang ,  Tong Qing Chen ,  Yong Kong Siew ,  Fan Zhang ,  San Leong Liew ,  John Sudijono ,  Liang Choo Hsia

Inventor： Johnny Widodo ,  Bei Chao Zhang ,  Tong Qing Chen ,  Yong Kong Siew ,  Fan Zhang ,  San Leong Liew ,  John Sudijono ,  Liang Choo Hsia

IPC: H01L21/4763

CPC classification number: H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/05073 ,  H01L2224/05546 ,  H01L2224/05647 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/01039 ,  H01L2924/00

Abstract: A method of forming a barrier layer and cap comprised of CuSiN for an interconnect. We provide an interconnect opening in a dielectric layer over a semiconductor structure. We form a CuSiN barrier layer over the sidewalls and bottom of the interconnect opening by reacting with the first copper layer. We then form an interconnect over the CuSiN layer filling the interconnect opening. We can form a CuSiN cap layer on the top surface of the interconnect.

Abstract translation: 形成用于互连的CuSiN构成的阻挡层和盖的方法。 我们在半导体结构上的电介质层中提供互连开口。 通过与第一铜层反应，在互连开口的侧壁和底部上形成CuSiN阻挡层。 然后，我们在填充互连开口的CuSiN层上形成互连。 我们可以在互连的顶部表面上形成CuSiN覆盖层。

公开(公告)号：US07294241B2

公开(公告)日：2007-11-13

申请号：US10336271

申请日：2003-01-03

Applicant: Chim Seng Seet ,  Bei Chao Zhang ,  San Leong Liew ,  John Sudijono ,  Lai Lin Clare Yong

Inventor： Chim Seng Seet ,  Bei Chao Zhang ,  San Leong Liew ,  John Sudijono ,  Lai Lin Clare Yong

IPC: C23C14/34 ,  H01L21/44

CPC classification number: H01L21/76843 ,  C23C14/165 ,  C23C14/541 ,  H01L21/2855 ,  H01L21/76846 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/0554 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/351 ,  Y10T428/12674 ,  Y10T428/12819 ,  Y10T428/12903 ,  H01L2924/00

Abstract: A method of sputtering a Ta layer comprised of alpha phase Ta on a Cu layer. An embodiment includes a Ta sputter deposition on a Cu surface at a substrate temperature less than 200° C. Another embodiment has a pre-cooling step at a temperature less than 100° C. prior to Ta layer sputter deposition. In another non-limiting example embodiment, a pre-clean step comprising an inert gas sputter is performed prior to the tantalum sputter. Another non-limiting example embodiment provides a semiconductor structure comprising: a semiconductor structure; a copper layer over the semiconductor structure; a tantalum layer on the copper layer; the tantalum layer comprised alpha phase Ta; a metal layer on the tantalum layer.

Abstract translation: 将由Al相Ta组成的Ta层溅射在Cu层上的方法。 一个实施方案包括在低于200℃的衬底温度下在Cu表面上的Ta溅射沉积。另一个实施方案在Ta层溅射沉积之前具有在低于100℃的温度下的预冷却步骤。 在另一个非限制性示例性实施例中，在钽溅射之前执行包括惰性气体溅射的预清洁步骤。 另一非限制性示例实施例提供一种半导体结构，包括：半导体结构; 半导体结构上的铜层; 铜层上的钽层; 钽层包括α相Ta; 钽层上的金属层。

公开(公告)号：US06995087B2

公开(公告)日：2006-02-07

申请号：US10328512

申请日：2002-12-23

Applicant: Wuping Liu ,  Juan Boon Tan ,  Bei Chao Zhang ,  Alan Cuthbertson

Inventor： Wuping Liu ,  Juan Boon Tan ,  Bei Chao Zhang ,  Alan Cuthbertson

IPC: H01L21/4763 ,  H01L21/44

CPC classification number: H01L21/76811 ,  H01L21/76813

Abstract: An integrated circuit manufacturing method includes providing a base, forming a first conductor, forming a first barrier layer, forming a first dielectric layer, and forming a masking layer. The method further including forming a first via opening in the masking layer, forming a first trench opening in the masking layer, and simultaneously forming a second via opening in a layer under the masking layer, and forming a second trench opening through the masking layer and in the layer under the masking layer and simultaneously forming a third via opening in another layer under the masking layer. The method further including removing the first barrier layer using the third via opening and the masking layer to form a trench and a via, and filling the trench and the via with a conductor to form a trench and via conductor in contact with the first conductor.

Abstract translation: 集成电路制造方法包括提供基底，形成第一导体，形成第一阻挡层，形成第一介电层，形成掩模层。 该方法还包括在掩模层中形成第一通孔，在掩模层中形成第一沟槽开口，同时在掩模层下方的层中形成第二通孔，并形成穿过掩模层的第二沟槽开口， 在掩模层下面的层中并且同时在掩模层下方的另一层中形成第三通孔。 该方法还包括使用第三通孔开口和掩模层去除第一阻挡层以形成沟槽和通孔，以及用导体填充沟槽和通孔以形成与第一导体接触的沟槽和通孔导体。

公开(公告)号：US08177993B2

公开(公告)日：2012-05-15

申请号：US11556696

申请日：2006-11-05

Applicant: Boon Meng Seah ,  Bei Chao Zhang ,  Raymond Joy ,  Shao Beng Law ,  John Sudijono ,  Liang Choo Hsia

Inventor： Boon Meng Seah ,  Bei Chao Zhang ,  Raymond Joy ,  Shao Beng Law ,  John Sudijono ,  Liang Choo Hsia

IPC: B44C1/22

CPC classification number: H01L21/67028 ,  H01L21/67051 ,  H01L21/6708

Abstract: An first example method and apparatus for etching and cleaning a substrate comprises device with a first manifold and a second manifold. The first manifold has a plurality of nozzles for dispensing chemicals onto the substrate. The second manifold is attached to a vacuum source and/or a dry air/gas source. A second example embodiment is a wafer cleaning device and method that uses a manifold with capillary jet nozzles and a liquid capillary jet stream to clean substrates.

Abstract translation: 用于蚀刻和清洁衬底的第一示例性方法和装置包括具有第一歧管和第二歧管的装置。 第一歧管具有用于将化学品分配到基底上的多个喷嘴。 第二歧管连接到真空源和/或干燥空气/气体源。 第二示例性实施例是晶片清洁装置和方法，其使用具有毛细管喷嘴和液体毛细管喷流的歧管来清洁基底。

公开(公告)号：US07947604B2

公开(公告)日：2011-05-24

申请号：US12019647

申请日：2008-01-25

Applicant: Fan Zhang ,  Lup San Leong ,  Yong Kong Siew ,  Bei Chao Zhang

Inventor： Fan Zhang ,  Lup San Leong ,  Yong Kong Siew ,  Bei Chao Zhang

IPC: H01L21/302

CPC classification number: B24B37/042 ,  B24B37/046

Abstract: The present invention relates to the reduction or complete prevention of Cu corrosion during a planarization or polishing process. In one aspect of the invention, RF signal is used to establish a negative bias in front of the wafer surface following polishing to eliminate Cu+ or Cu2+ migrations. In another aspect of the invention, a DC Voltage power supply is used to establish the negative bias.

Abstract translation: 本发明涉及在平坦化或抛光过程中减少或完全防止Cu腐蚀。 在本发明的一个方面中，RF信号用于在抛光之后在晶片表面前建立负偏压以消除Cu +或Cu 2+迁移。 在本发明的另一方面，使用DC电压电源来建立负偏压。

公开(公告)号：US06517235B2

公开(公告)日：2003-02-11

申请号：US09867560

申请日：2001-05-31

Applicant: Zhong Yun Zhu ,  Rajneesh Jaiswal ,  Haznita Abd Karim ,  Bei Chao Zhang ,  Johnny Cham ,  Ravi Sankar Yelamanchi ,  Chee Kong Leong

Inventor： Zhong Yun Zhu ,  Rajneesh Jaiswal ,  Haznita Abd Karim ,  Bei Chao Zhang ,  Johnny Cham ,  Ravi Sankar Yelamanchi ,  Chee Kong Leong

IPC: G01K1700

CPC classification number: G01K15/002

Abstract: A method for controlling and/or calibrating rapid thermal process systems is described. One or more wafers comprising a silicon semiconductor substrate having a refractory metal layer thereon are silicided in a RTP system at different temperatures. Sheet resistance uniformity of the wafer is measured thereby detecting silicidation phase transition temperature points at the highest uniformity points. The temperature points are used to calibrate or to reset the RTP system. A plurality of wafers comprising a silicon semiconductor substrate having a refractory metal layer thereon can be silicided in each of a plurality of rapid thermal process systems. Sheet resistance uniformity of each of the wafers is measured thereby detecting silicidation phase transition temperature points by highest sheet resistance uniformity for each of the RTP systems. The temperature points are used to match temperatures for each of the RTP systems. The temperature point depend upon the type of refractory metal used and can range from about 200 to 800 ° C.

Abstract translation: 描述了用于控制和/或校准快速热处理系统的方法。 包括其上具有难熔金属层的硅半导体衬底的一个或多个晶片在不同温度的RTP系统中被硅化。 测量晶片的片电阻均匀性，从而检测最高均匀点处的硅化相变温度点。 温度点用于校准或复位RTP系统。 包括其上具有难熔金属层的硅半导体衬底的多个晶片可以在多个快速热处理系统中的每一个中被硅化。 测量每个晶片的薄片电阻均匀性，从而通过每个RTP系统的最高薄层电阻均匀性来检测硅化相变温度点。 温度点用于匹配每个RTP系统的温度。 温度点取决于使用的难熔金属的类型，可以在约200至800℃的范围内

公开(公告)号：US08115276B2

公开(公告)日：2012-02-14

申请号：US12132342

申请日：2008-06-03

Applicant: Shaoqing Zhang ,  Fan Zhang ,  Shao-fu Sanford Chu ,  Bei Chao Zhang

Inventor： Shaoqing Zhang ,  Fan Zhang ,  Shao-fu Sanford Chu ,  Bei Chao Zhang

IPC: H01L21/283 ,  H01L21/02 ,  H01L29/92

CPC classification number: H01L27/0207 ,  H01L21/76816 ,  H01L23/5223 ,  H01L23/5226 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit system that includes: providing a substrate including front-end-of-line circuitry; forming a first metallization layer over the substrate and electrically connected to the substrate; forming a viabar or a via group over the first metallization layer; and forming a second metallization layer over the first metallization layer and electrically connected to the first metallization layer through either the viabar or the via group.

Abstract translation: 一种集成电路系统，包括：提供包括前端电路的基板; 在所述衬底上形成第一金属化层并电连接至所述衬底; 在所述第一金属化层上形成viabar或通孔基团; 以及在所述第一金属化层上形成第二金属化层，并且通过所述viabar或通孔基团电连接到所述第一金属化层。

公开(公告)号：US07803704B2

公开(公告)日：2010-09-28

申请号：US12196291

申请日：2008-08-22

Applicant: Bei Chao Zhang ,  Chim Seng Seet ,  Juan Boon Tan ,  Fan Zhang ,  Yong Chiang Ee ,  Bo Tao ,  Tong Qing Chen ,  Liang Choo Hsia

Inventor： Bei Chao Zhang ,  Chim Seng Seet ,  Juan Boon Tan ,  Fan Zhang ,  Yong Chiang Ee ,  Bo Tao ,  Tong Qing Chen ,  Liang Choo Hsia

IPC: H01L21/4763

CPC classification number: H01L23/5329 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with a dielectric layer formed thereon. The dielectric layer having a conductive line disposed in an upper portion of the dielectric layer. The substrate is processed to produce a top surface of the dielectric layer that is not coplanar with a top surface of the conductive line to form a stepped topography.

Abstract translation: 提出了一种形成半导体器件的方法。 该方法包括提供用其上形成的电介质层制备的衬底。 电介质层具有布置在电介质层上部的导线。 处理衬底以产生与导电线的顶表面不共面的电介质层的顶表面，以形成阶梯形状。