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    Spacer profile engineering using films with continuously increased etch rate from inner to outer surface
    1.
    发明授权
    Spacer profile engineering using films with continuously increased etch rate from inner to outer surface 有权
    使用具有从内到外表面的不断增加的蚀刻速率的膜的间隔轮廓工程

    公开(公告)号：US08828858B2

    公开(公告)日：2014-09-09

    申请号：US13353684

    申请日：2012-01-19

    申请人： Xuesong Rao ,  Chim Seng Seet ,  Hai Cong ,  Zheng Zou ,  Alex See ,  Yun Ling Tan ,  Wen Zhan Zhou ,  Lup San Leong

    发明人： Xuesong Rao ,  Chim Seng Seet ,  Hai Cong ,  Zheng Zou ,  Alex See ,  Yun Ling Tan ,  Wen Zhan Zhou ,  Lup San Leong

    IPC分类号： H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L29/6653 ,  H01L29/6656

    摘要： Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode and substrate, the spacer layer having a first surface nearest the gate electrode and substrate, a second surface furthest from the gate electrode and substrate, and a continuously increasing etch rate from the first surface to the second surface, and etching the spacer layer to form a spacer on each side of the gate electrode. Embodiments further include forming the spacer layer by depositing a spacer material and continuously decreasing the density of the spacer material during deposition or depositing a carbon-containing spacer material and causing a gradient of carbon content in the spacer layer.

    摘要翻译： 通过形成具有锥形轮廓的栅极间隔物来增强层间电介质间隙填充工艺。 实施例包括在衬底上形成栅电极，在栅电极和衬底上沉积间隔物材料，间隔层具有最靠近栅电极和衬底的第一表面，离栅电极和衬底最远的第二表面，以及连续增加 从第一表面到第二表面的蚀刻速率，并且蚀刻间隔层以在栅电极的每一侧上形成间隔物。 实施例还包括通过沉积间隔物材料形成间隔层，并在沉积期间连续降低间隔物材料的密度或沉积含碳间隔物材料并引起间隔层中的碳含量梯度。

    Step-like spacer profile
    3.
    发明授权
    Step-like spacer profile 有权
    阶梯状间隔剖面

    公开(公告)号：US08492236B1

    公开(公告)日：2013-07-23

    申请号：US13348766

    申请日：2012-01-12

    申请人： Xuesong Rao ,  Chim Seng Seet ,  Hai Cong ,  Zheng Zou ,  Alex See ,  Yun Ling Tan ,  Wen Zhan Zhou ,  Lup San Leong ,  Huang Liu

    发明人： Xuesong Rao ,  Chim Seng Seet ,  Hai Cong ,  Zheng Zou ,  Alex See ,  Yun Ling Tan ,  Wen Zhan Zhou ,  Lup San Leong ,  Huang Liu

    IPC分类号： H01L21/336

    CPC分类号： H01L29/6656 ,  H01L29/78

    摘要： Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a step-like or tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode, etching the spacer material to form a first spacer on each side of the gate electrode, and pulling back the first spacers to form second spacers which have a step-like profile. Embodiments further include depositing a second spacer material over the gate electrode and the second spacers, and etching the second spacer material to form a third spacer on each second spacer, the second and third spacers forming an outwardly tapered composite spacer.

    摘要翻译： 通过形成具有阶梯状或锥形轮廓的栅极间隔物来增强层间电介质间隙填充工艺。 实施例包括在衬底上形成栅电极，在栅电极上沉积间隔物材料，蚀刻间隔物材料以在栅电极的每一侧上形成第一间隔物，并拉回第一间隔物以形成第二间隔物， 像个人资料 实施例还包括在栅极电极和第二间隔物上沉积第二间隔物材料，并蚀刻第二间隔物材料以在每个第二间隔物上形成第三间隔物，第二和第三间隔物形成向外锥形的复合间隔物。

    Integrated circuit system using dual damascene process
    5.
    发明授权
    Integrated circuit system using dual damascene process 有权
    集成电路系统采用双镶嵌工艺

    公开(公告)号：US07253097B2

    公开(公告)日：2007-08-07

    申请号：US11160624

    申请日：2005-06-30

    申请人： Yeow Kheng Lim ,  Chim Seng Seet ,  Tae Jong Lee ,  Liang-Choo Hsia ,  Kin Leong Pey

    发明人： Yeow Kheng Lim ,  Chim Seng Seet ,  Tae Jong Lee ,  Liang-Choo Hsia ,  Kin Leong Pey

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76831 ,  H01L21/76814 ,  H01L21/76844 ,  H01L21/76846

    摘要： An integrated circuit system includes providing a semiconductor substrate having a semiconductor device provided thereon. A first dielectric layer is formed over the semiconductor substrate, and a first conductor core is formed in the first dielectric layer. A stop layer is formed over the first conductor core. A second dielectric layer is formed over the stop layer. A channel and a via are formed in the second dielectric layer. The channel and the via in the second dielectric layer are wet cleaned. A barrier metal layer is deposited to line the channel and the via in the second dielectric layer. The barrier metal layer is selectively etched from the bottom of the via in the dielectric layer, and a second conductor core is formed over the barrier metal layer to fill the second channel and the via to connect the second conductor core to the first conductor core.

    摘要翻译： 集成电路系统包括提供其上设置有半导体器件的半导体衬底。 第一电介质层形成在半导体衬底之上，并且第一导体芯形成在第一电介质层中。 在第一导体芯上形成停止层。 在停止层上形成第二电介质层。 在第二电介质层中形成沟道和通孔。 第二介质层中的通道和通孔被湿清洗。 沉积阻挡金属层以在第二介电层中对通道和通孔进行排列。 从电介质层中的通孔的底部选择性地蚀刻阻挡金属层，并且在阻挡金属层上方形成第二导体芯以填充第二通道和通孔，以将第二导体芯连接到第一导体芯。

    INTEGRATED CIRCUIT SYSTEM USING DUAL DAMASCENE PROCESS
    6.
    发明申请
    INTEGRATED CIRCUIT SYSTEM USING DUAL DAMASCENE PROCESS 有权
    集成电路系统使用双重DAMASCENE过程

    公开(公告)号：US20070001303A1

    公开(公告)日：2007-01-04

    申请号：US11160624

    申请日：2005-06-30

    申请人： Yeow Kheng Lim ,  Chim Seng Seet ,  Tae Jong Lee ,  Liang-Choo Hsia ,  Kin Leong Pey

    发明人： Yeow Kheng Lim ,  Chim Seng Seet ,  Tae Jong Lee ,  Liang-Choo Hsia ,  Kin Leong Pey

    IPC分类号： H01L23/52

    CPC分类号： H01L21/76831 ,  H01L21/76814 ,  H01L21/76844 ,  H01L21/76846

    摘要： An integrated circuit system includes providing a semiconductor substrate having a semiconductor device provided thereon. A first dielectric layer is formed over the semiconductor substrate, and a first conductor core is formed in the first dielectric layer. A stop layer is formed over the first conductor core. A second dielectric layer is formed over the stop layer. A channel and a via are formed in the second dielectric layer. The channel and the via in the second dielectric layer are wet cleaned. A barrier metal layer is deposited to line the channel and the via in the second dielectric layer. The barrier metal layer is selectively etched from the bottom of the via in the dielectric layer, and a second conductor core is formed over the barrier metal layer to fill the second channel and the via to connect the second conductor core to the first conductor core.

    摘要翻译： 集成电路系统包括提供其上设置有半导体器件的半导体衬底。 第一电介质层形成在半导体衬底之上，并且第一导体芯形成在第一电介质层中。 在第一导体芯上形成停止层。 在停止层上形成第二电介质层。 在第二电介质层中形成沟道和通孔。 第二介质层中的通道和通孔被湿清洗。 沉积阻挡金属层以在第二介电层中对通道和通孔进行排列。 从电介质层中的通孔的底部选择性地蚀刻阻挡金属层，并且在阻挡金属层上方形成第二导体芯以填充第二通道和通孔，以将第二导体芯连接到第一导体芯。

    SPACER PROFILE ENGINEERING USING FILMS WITH CONTINUOUSLY INCREASED ETCH RATE FROM INNER TO OUTER SURFACE
    7.
    发明申请
    SPACER PROFILE ENGINEERING USING FILMS WITH CONTINUOUSLY INCREASED ETCH RATE FROM INNER TO OUTER SURFACE 有权
    使用膜的间隙轮廓工程，从内部到外表面连续增加的刻蚀速率

    公开(公告)号：US20130187202A1

    公开(公告)日：2013-07-25

    申请号：US13353684

    申请日：2012-01-19

    申请人： Xuesong Rao ,  Chim Seng Seet ,  Hai Cong ,  Zheng Zou ,  Alex See ,  Yun Ling Tan ,  Wen Zhan Zhou ,  Lup San Leong

    发明人： Xuesong Rao ,  Chim Seng Seet ,  Hai Cong ,  Zheng Zou ,  Alex See ,  Yun Ling Tan ,  Wen Zhan Zhou ,  Lup San Leong

    IPC分类号： H01L29/78 ,  H01L21/28

    CPC分类号： H01L29/6653 ,  H01L29/6656

    摘要： Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode and substrate, the spacer layer having a first surface nearest the gate electrode and substrate, a second surface furthest from the gate electrode and substrate, and a continuously increasing etch rate from the first surface to the second surface, and etching the spacer layer to form a spacer on each side of the gate electrode. Embodiments further include forming the spacer layer by depositing a spacer material and continuously decreasing the density of the spacer material during deposition or depositing a carbon-containing spacer material and causing a gradient of carbon content in the spacer layer.

    摘要翻译： 通过形成具有锥形轮廓的栅极间隔物来增强层间电介质间隙填充工艺。 实施例包括在衬底上形成栅电极，在栅电极和衬底上沉积间隔物材料，间隔层具有最靠近栅电极和衬底的第一表面，离栅电极和衬底最远的第二表面，以及连续增加 从第一表面到第二表面的蚀刻速率，并且蚀刻间隔层以在栅电极的每一侧上形成间隔物。 实施例还包括通过沉积间隔物材料形成间隔层，并在沉积期间连续降低间隔物材料的密度或沉积含碳间隔物材料并引起间隔层中的碳含量梯度。

    STEP-LIKE SPACER PROFILE
    8.
    发明申请
    STEP-LIKE SPACER PROFILE 有权

    公开(公告)号：US20130181259A1

    公开(公告)日：2013-07-18

    申请号：US13348766

    申请日：2012-01-12

    申请人： Xuesong Rao ,  Chim Seng Seet ,  Hai Cong ,  Zheng Zou ,  Alex See ,  Yun Ling Tan ,  Wen Zhan Zhou ,  Lup San Leong ,  Huang Liu

    发明人： Xuesong Rao ,  Chim Seng Seet ,  Hai Cong ,  Zheng Zou ,  Alex See ,  Yun Ling Tan ,  Wen Zhan Zhou ,  Lup San Leong ,  Huang Liu

    IPC分类号： H01L29/78 ,  H01L21/28

    CPC分类号： H01L29/6656 ,  H01L29/78

    摘要： Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a step-like or tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode, etching the spacer material to form a first spacer on each side of the gate electrode, and pulling back the first spacers to form second spacers which have a step-like profile. Embodiments further include depositing a second spacer material over the gate electrode and the second spacers, and etching the second spacer material to form a third spacer on each second spacer, the second and third spacers forming an outwardly tapered composite spacer.

    摘要翻译： 通过形成具有阶梯状或锥形轮廓的栅极间隔物来增强层间电介质间隙填充工艺。 实施例包括在衬底上形成栅电极，在栅电极上沉积间隔物材料，蚀刻间隔物材料以在栅电极的每一侧上形成第一间隔物，并拉回第一间隔物以形成第二间隔物， 像个人资料 实施例还包括在栅极电极和第二间隔物上沉积第二间隔物材料，并蚀刻第二间隔物材料以在每个第二间隔物上形成第三间隔物，第二和第三间隔物形成向外锥形的复合间隔物。

    METHOD OF FORMING OXIDE ENCAPSULATED CONDUCTIVE FEATURES
    9.
    发明申请
    METHOD OF FORMING OXIDE ENCAPSULATED CONDUCTIVE FEATURES 审中-公开
    形成氧化物导电性能的方法

    公开(公告)号：US20120273949A1

    公开(公告)日：2012-11-01

    申请号：US13095140

    申请日：2011-04-27

    申请人： Huang Liu ,  Chim Seng Seet ,  Alex Kai Hung See

    发明人： Huang Liu ,  Chim Seng Seet ,  Alex Kai Hung See

    IPC分类号： H01L23/52 ,  H01L21/768

    CPC分类号： H01L23/53238 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76873 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Semiconductor devices are formed with a Cu or Cu alloy interconnect encapsulated by a substantially uniform MnO or Al2O3 layer. Embodiments include forming an opening having side surfaces and a bottom surface in a dielectric layer, forming a barrier layer on the side surfaces and the bottom surface of the opening and on an upper surface of the dielectric layer, treating the barrier layer with an oxygen plasma to form dangling oxygen atoms on the barrier layer, depositing a seed layer on the barrier layer, and filling the opening with Cu or a Cu alloy.

    摘要翻译： 半导体器件由具有基本上均匀的MnO或Al 2 O 3层封装的Cu或Cu合金互连形成。 实施例包括在电介质层中形成具有侧表面和底表面的开口，在开口的侧表面和底表面以及电介质层的上表面上形成阻挡层，用氧等离子体处理阻挡层 在阻挡层上形成悬浮的氧原子，在阻挡层上沉积种子层，并用Cu或Cu合金填充开口。