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    SPACER PROFILE ENGINEERING USING FILMS WITH CONTINUOUSLY INCREASED ETCH RATE FROM INNER TO OUTER SURFACE
    1.
    发明申请
    SPACER PROFILE ENGINEERING USING FILMS WITH CONTINUOUSLY INCREASED ETCH RATE FROM INNER TO OUTER SURFACE 有权
    使用膜的间隙轮廓工程，从内部到外表面连续增加的刻蚀速率

    公开(公告)号：US20130187202A1

    公开(公告)日：2013-07-25

    申请号：US13353684

    申请日：2012-01-19

    申请人： Xuesong Rao ,  Chim Seng Seet ,  Hai Cong ,  Zheng Zou ,  Alex See ,  Yun Ling Tan ,  Wen Zhan Zhou ,  Lup San Leong

    发明人： Xuesong Rao ,  Chim Seng Seet ,  Hai Cong ,  Zheng Zou ,  Alex See ,  Yun Ling Tan ,  Wen Zhan Zhou ,  Lup San Leong

    IPC分类号： H01L29/78 ,  H01L21/28

    CPC分类号： H01L29/6653 ,  H01L29/6656

    摘要： Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode and substrate, the spacer layer having a first surface nearest the gate electrode and substrate, a second surface furthest from the gate electrode and substrate, and a continuously increasing etch rate from the first surface to the second surface, and etching the spacer layer to form a spacer on each side of the gate electrode. Embodiments further include forming the spacer layer by depositing a spacer material and continuously decreasing the density of the spacer material during deposition or depositing a carbon-containing spacer material and causing a gradient of carbon content in the spacer layer.

    摘要翻译： 通过形成具有锥形轮廓的栅极间隔物来增强层间电介质间隙填充工艺。 实施例包括在衬底上形成栅电极，在栅电极和衬底上沉积间隔物材料，间隔层具有最靠近栅电极和衬底的第一表面，离栅电极和衬底最远的第二表面，以及连续增加 从第一表面到第二表面的蚀刻速率，并且蚀刻间隔层以在栅电极的每一侧上形成间隔物。 实施例还包括通过沉积间隔物材料形成间隔层，并在沉积期间连续降低间隔物材料的密度或沉积含碳间隔物材料并引起间隔层中的碳含量梯度。

    STEP-LIKE SPACER PROFILE
    2.
    发明申请
    STEP-LIKE SPACER PROFILE 有权

    公开(公告)号：US20130181259A1

    公开(公告)日：2013-07-18

    申请号：US13348766

    申请日：2012-01-12

    申请人： Xuesong Rao ,  Chim Seng Seet ,  Hai Cong ,  Zheng Zou ,  Alex See ,  Yun Ling Tan ,  Wen Zhan Zhou ,  Lup San Leong ,  Huang Liu

    发明人： Xuesong Rao ,  Chim Seng Seet ,  Hai Cong ,  Zheng Zou ,  Alex See ,  Yun Ling Tan ,  Wen Zhan Zhou ,  Lup San Leong ,  Huang Liu

    IPC分类号： H01L29/78 ,  H01L21/28

    CPC分类号： H01L29/6656 ,  H01L29/78

    摘要： Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a step-like or tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode, etching the spacer material to form a first spacer on each side of the gate electrode, and pulling back the first spacers to form second spacers which have a step-like profile. Embodiments further include depositing a second spacer material over the gate electrode and the second spacers, and etching the second spacer material to form a third spacer on each second spacer, the second and third spacers forming an outwardly tapered composite spacer.

    摘要翻译： 通过形成具有阶梯状或锥形轮廓的栅极间隔物来增强层间电介质间隙填充工艺。 实施例包括在衬底上形成栅电极，在栅电极上沉积间隔物材料，蚀刻间隔物材料以在栅电极的每一侧上形成第一间隔物，并拉回第一间隔物以形成第二间隔物， 像个人资料 实施例还包括在栅极电极和第二间隔物上沉积第二间隔物材料，并蚀刻第二间隔物材料以在每个第二间隔物上形成第三间隔物，第二和第三间隔物形成向外锥形的复合间隔物。

    Novel method to control dual damascene trench etch profile and trench depth uniformity
    4.
    发明申请
    Novel method to control dual damascene trench etch profile and trench depth uniformity 有权
    控制双镶嵌沟槽蚀刻轮廓和沟槽深度均匀性的新方法

    公开(公告)号：US20050170625A1

    公开(公告)日：2005-08-04

    申请号：US10767292

    申请日：2004-01-29

    申请人： Hai Cong ,  Yong Siew ,  Liang Hsia

    发明人： Hai Cong ,  Yong Siew ,  Liang Hsia

    IPC分类号： H01L21/44 ,  H01L21/768

    CPC分类号： H01L21/76808

    摘要： A method of forming trench openings in a dual damascene trench and via etch process by using a two component hard mask layer, termed a bi-layer, over different intermetal dielectrics, IMD, to solve dual damascene patterning problems, such as, fencing and sub-trench formation. Via first patterning in dual damascene processing is one of the major integration schemes for copper backend of line (BEOL) integration. Via first dual damascene scheme usually uses a hard mask layer deposited on top of an inter-metal dielectric (IMD) film stack. The dual damascene trench etch requires uniform trench depth across wafer after etch. In addition, via top corner profiles need to be well maintained without any fencing or faceting. The present method solves these problems by using a two component hard mask layer, termed a bi-layer, deposited directly on top of an inter-metal dielectric (IMD) film stack.

    摘要翻译： 一种在双镶嵌沟槽和通孔蚀刻工艺中形成沟槽开口的方法，其通过使用称为双层的双组分硬掩模层在不同的金属间电介质IMD之间，以解决双镶嵌图案化问题，例如栅栏和子 螺旋形成。 通过在双镶嵌处理​​中的首次图案化是铜后端（BEOL）集成的主要集成方案之一。 通过第一双镶嵌方案通常使用沉积在金属间电介质（IMD）膜堆叠顶部上的硬掩模层。 双镶嵌沟槽蚀刻需要在蚀刻后跨晶片的均匀沟槽深度。 此外，通过顶角型材需要维护良好，没有任何围栏或小面。 本方法通过使用直接沉积在金属间电介质（IMD）膜堆叠的顶部上的双组分硬掩模层来解决这些问题。

    Integration of eNVM, RMG, and HKMG modules
    6.
    发明授权
    Integration of eNVM, RMG, and HKMG modules 有权
    集成eNVM，RMG和HKMG模块

    公开(公告)号：US08518775B2

    公开(公告)日：2013-08-27

    申请号：US13251444

    申请日：2011-10-03

    申请人： Huang Liu ,  Alex Kai Hung See ,  Hai Cong ,  Zheng Zou

    发明人： Huang Liu ,  Alex Kai Hung See ,  Hai Cong ,  Zheng Zou

    IPC分类号： H01L21/336 ,  H01L29/66

    CPC分类号： H01L21/823456 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823878 ,  H01L27/11546 ,  H01L29/66545

    摘要： A memory device is fabricated through the integration of embedded non-volatile memory (eNVM) with replacement metal gate (RMG) and high-k/metal gate (HKMG) modules. Embodiments include forming two substrate portions having upper surfaces at different heights, forming non-volatile gate stacks over the substrate portion with the lower upper surface, and forming high-voltage gate stacks and logic gate stacks over the other substrate portion. Embodiments include the upper surfaces of the non-voltage gate stacks, the high-voltage gate stacks, and the logic gate stacks being substantially coplanar.

    摘要翻译： 通过将嵌入式非易失性存储器（eNVM）与替代金属栅极（RMG）和高k /金属栅极（HKMG）模块集成来制造存储器件。 实施例包括形成具有不同高度的上表面的两个基板部分，在具有下上表面的基板部分上形成非易失性栅极堆叠，以及在另一个基板部分上形成高压栅极堆叠和逻辑栅极堆叠。 实施例包括非电压栅极堆叠的上表面，高压栅极堆叠以及基本共面的逻辑门叠层。

    INTEGRATION OF eNVM, RMG, AND HKMG MODULES
    7.
    发明申请
    INTEGRATION OF eNVM, RMG, AND HKMG MODULES 有权
    整合eNVM，RMG和HKMG模块

    公开(公告)号：US20130082318A1

    公开(公告)日：2013-04-04

    申请号：US13251444

    申请日：2011-10-03

    申请人： Huang Liu ,  Alex Kai Hung See ,  Hai Cong ,  Zheng Zou

    发明人： Huang Liu ,  Alex Kai Hung See ,  Hai Cong ,  Zheng Zou

    IPC分类号： H01L29/792 ,  H01L21/762

    CPC分类号： H01L21/823456 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823878 ,  H01L27/11546 ,  H01L29/66545

    摘要： A memory device is fabricated through the integration of embedded non-volatile memory (eNVM) with replacement metal gate (RMG) and high-k/metal gate (HKMG) modules. Embodiments include forming two substrate portions having upper surfaces at different heights, forming non-volatile gate stacks over the substrate portion with the lower upper surface, and forming high-voltage gate stacks and logic gate stacks over the other substrate portion. Embodiments include the upper surfaces of the non-voltage gate stacks, the high-voltage gate stacks, and the logic gate stacks being substantially coplanar.

    摘要翻译： 通过将嵌入式非易失性存储器（eNVM）与替代金属栅极（RMG）和高k /金属栅极（HKMG）模块集成来制造存储器件。 实施例包括形成具有不同高度的上表面的两个基板部分，在具有下上表面的基板部分上形成非易失性栅极堆叠，以及在另一个基板部分上形成高压栅极堆叠和逻辑栅极堆叠。 实施例包括非电压栅极堆叠的上表面，高压栅极堆叠以及基本共面的逻辑门叠层。