公开(公告)号：US20140008810A1

公开(公告)日：2014-01-09

申请号：US13542256

申请日：2012-07-05

申请人： Lup San Leong ,  Zheng Zou ,  Alex Kai Hung See ,  Hai Cong ,  Xuesong Rao ,  Yun Ling Tan ,  Huang Liu

发明人： Lup San Leong ,  Zheng Zou ,  Alex Kai Hung See ,  Hai Cong ,  Xuesong Rao ,  Yun Ling Tan ,  Huang Liu

IPC分类号： H01L21/306 ,  H01L23/48

CPC分类号： H01L23/481 ,  H01L21/02107 ,  H01L21/486 ,  H01L21/76898 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13009 ,  H01L2224/1357

摘要： Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.

摘要翻译： 具有贯通硅通孔（TSV）的半导体器件不形成铜污染。 实施例包括在硅衬底中暴露围绕TSV的底部的钝化层，在暴露的钝化层上方并在硅衬底的底表面上形成硅复合层，在硅复合层上形成硬掩模层， 硅衬底的底表面，使用硬掩模层作为掩模去除围绕TSV的底部部分的硅复合层的一部分，再次暴露钝化层，以及将硬掩模层和再曝光的钝化层移除到 暴露TSV底部的触点。

公开(公告)号：US08572524B2

公开(公告)日：2013-10-29

申请号：US11943591

申请日：2007-11-21

申请人： Wenzhan Zhou ,  Liang Choo Hsia ,  Meisheng Zhou ,  Zheng Zou

发明人： Wenzhan Zhou ,  Liang Choo Hsia ,  Meisheng Zhou ,  Zheng Zou

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： An optical proximity correction (OPC) model incorporates inline process variation data. OPC is performed by adjusting an input mask pattern with a mask bias derived from the OPC model to correct errors in the input mask pattern.

摘要翻译： 光学邻近校正（OPC）模型包含在线过程变化数据。 通过使用从OPC模型导出的掩模偏差调整输入掩模图案来校正输入掩模图案中的错误来执行OPC。

公开(公告)号：US06632745B1

公开(公告)日：2003-10-14

申请号：US10222387

申请日：2002-08-16

申请人： Chiew Wah Yap ,  Zheng Zou ,  Eng Hua Lim ,  Nguyen Lac ,  Yelehanka Pradeep ,  Manni Lal

发明人： Chiew Wah Yap ,  Zheng Zou ,  Eng Hua Lim ,  Nguyen Lac ,  Yelehanka Pradeep ,  Manni Lal

IPC分类号： H01L21311

CPC分类号： H01L29/6653 ,  H01L29/665

摘要： A patterned and etched layer of gate electrode material is formed over the active surface of a substrate, a layer of liner oxide is created, gate spacers are created. Under the first embodiment of the invention, a layer of TEOS is deposited over the created structure over which a layer of nitride is deposited, The layer of nitride is etched, this etch is extended into an overetch creating openings through the layer of TEOS where this layer overlies the gate spacers. The gate spacers are then further etched. Under the second embodiment of the invention, a layer of TEOS is deposited over the created structure. The layer of TEOS is etched, stopping on the silicon nitride of the gate spacers. The gate spacers are then further etched.

摘要翻译： 在衬底的有源表面上形成图案化和蚀刻的栅极材料层，形成衬垫氧化物层，形成栅极间隔物。在本发明的第一个实施方案中，存在一层TEOS 在其上沉积氮化物层的所产生的结构上。蚀刻氮化物层，该蚀刻扩展到通过TEOS层产生开口的过蚀刻，其中该层覆盖在栅极间隔物上。 然后进一步蚀刻栅极间隔物。在本发明的第二实施例中，在所创建的结构上沉积TEOS层。 蚀刻TEOS层，停留在栅极间隔物的氮化硅上。 然后进一步蚀刻栅极间隔物

公开(公告)号：US09034720B2

公开(公告)日：2015-05-19

申请号：US13588018

申请日：2012-08-17

申请人： Hui Liu ,  Wen Zhan Zhou ,  Zheng Zou ,  Qun Ying Lin ,  Alex Kai Hung See

发明人： Hui Liu ,  Wen Zhan Zhou ,  Zheng Zou ,  Qun Ying Lin ,  Alex Kai Hung See

IPC分类号： H01L21/76 ,  G02B6/136 ,  G03F7/20 ,  G02B6/124

CPC分类号： G02B6/136 ,  G02B6/124 ,  G03F7/70633

摘要： A method and a device are provided for diffracting incident light from a lithographic scanner in an IC process flow. Embodiments include forming a diffraction grating in a first layer on a semiconductor substrate; and forming a plurality of lithographic alignment marks in a second layer, overlying the first layer, wherein the diffraction grating has a width and a length greater than or equal to a width and length, respectively, of the plurality of lithographic alignment marks.

摘要翻译： 提供了一种用于在IC工艺流程中衍射来自光刻扫描仪的入射光的方法和装置。 实施例包括在半导体衬底上的第一层中形成衍射光栅; 以及在覆盖所述第一层的第二层中形成多个平版印刷对准标记，其中所述衍射光栅的宽度和长度分别大于或等于所述多个平版印刷对准标记的宽度和长度。

公开(公告)号：US06281093B1

公开(公告)日：2001-08-28

申请号：US09619016

申请日：2000-07-19

申请人： Yelehanka Ramachandramurthy Pradeep ,  Qinghua Zhong ,  Zheng Zou ,  Henry Gerung

发明人： Yelehanka Ramachandramurthy Pradeep ,  Qinghua Zhong ,  Zheng Zou ,  Henry Gerung

IPC分类号： H01L2176

CPC分类号： H01L21/76237 ,  H01L21/76224

摘要： A new method of fabricating shallow trench isolations has been achieved. A silicon dioxide layer is formed overlying a semiconductor substrate. A silicon nitride layer is deposited overlying the silicon dioxide layer. The silicon nitride layer is patterned to expose the semiconductor substrate where shallow trench isolations are planned. Ions are implanted into the exposed semiconductor substrate. The implanting damages any passive surface materials overlying the semiconductor substrate. The exposed semiconductor substrate is etched down to form trenches. The damaged passive surface materials are removed during the etching down to thereby prevent trench cone formation. A trench filling layer is deposited to fill the trenches. The trench filling layer is polished down to complete the shallow trench isolations in the manufacture of the integrated circuit device.

摘要翻译： 已经实现了制造浅沟槽隔离的新方法。 在半导体衬底上形成二氧化硅层。 沉积氮化硅层覆盖二氧化硅层。 图案化氮化硅层以暴露其中规划浅沟槽隔离的半导体衬底。 将离子注入到暴露的半导体衬底中。 植入损伤覆盖半导体衬底的任何被动表面材料。 暴露的半导体衬底被蚀刻以形成沟槽。 在蚀刻期间，损坏的被动表面材料被去除，从而防止形成沟槽。 沉积沟槽填充层以填充沟槽。 在集成电路器件的制造中，沟槽填充层被抛光以完成浅沟槽隔离。

公开(公告)号：US08852968B2

公开(公告)日：2014-10-07

申请号：US13768870

申请日：2013-02-15

申请人： Liang Li ,  Zheng Zou ,  Huang Liu ,  Alex See

发明人： Liang Li ,  Zheng Zou ,  Huang Liu ,  Alex See

IPC分类号： H01L21/66

CPC分类号： H01L22/12 ,  G01B2210/56

摘要： Methods of deducing oxide thickness using calculated and measured scattering spectra are provided. Embodiments include depositing an oxide over a semiconductor wafer, reducing the oxide from a portion of the semiconductor wafer, and deducing a thickness of oxide remaining at a location within the portion using scatterometric metrology. Embodiments further include deducing the thickness by: calculating scattering spectra for a plurality of oxide thicknesses, producing calculated scattering spectra, monitoring scattering spectra at the location within the portion of the semiconductor wafer, comparing the monitored scattering spectra at the location to the calculated scattering spectra, determining a closest matching calculated scattering spectra to the monitored scattering spectra at the location, and obtaining an oxide thickness corresponding to the closest matching calculated scattering spectra.

摘要翻译： 提供了使用计算和测量的散射光谱推导氧化物厚度的方法。 实施例包括在半导体晶片上沉积氧化物，从半导体晶片的一部分还原氧化物，并使用散射测量法推算残留在该部分内部的氧化物的厚度。 实施例还包括通过以下方式推导厚度：计算多个氧化物厚度的散射光谱，产生计算的散射光谱，监测半导体晶片部分内的位置处的散射光谱，将该位置处的所监视的散射光谱与计算出的散射光谱进行比较 确定与所述位置处的所监视的散射光谱最接近的匹配计算的散射光谱，以及获得对应于最接近的匹配计算的散射光谱的氧化物厚度。

公开(公告)号：US08518775B2

公开(公告)日：2013-08-27

申请号：US13251444

申请日：2011-10-03

申请人： Huang Liu ,  Alex Kai Hung See ,  Hai Cong ,  Zheng Zou

发明人： Huang Liu ,  Alex Kai Hung See ,  Hai Cong ,  Zheng Zou

IPC分类号： H01L21/336 ,  H01L29/66

CPC分类号： H01L21/823456 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823878 ,  H01L27/11546 ,  H01L29/66545

摘要： A memory device is fabricated through the integration of embedded non-volatile memory (eNVM) with replacement metal gate (RMG) and high-k/metal gate (HKMG) modules. Embodiments include forming two substrate portions having upper surfaces at different heights, forming non-volatile gate stacks over the substrate portion with the lower upper surface, and forming high-voltage gate stacks and logic gate stacks over the other substrate portion. Embodiments include the upper surfaces of the non-voltage gate stacks, the high-voltage gate stacks, and the logic gate stacks being substantially coplanar.

摘要翻译： 通过将嵌入式非易失性存储器（eNVM）与替代金属栅极（RMG）和高k /金属栅极（HKMG）模块集成来制造存储器件。 实施例包括形成具有不同高度的上表面的两个基板部分，在具有下上表面的基板部分上形成非易失性栅极堆叠，以及在另一个基板部分上形成高压栅极堆叠和逻辑栅极堆叠。 实施例包括非电压栅极堆叠的上表面，高压栅极堆叠以及基本共面的逻辑门叠层。

公开(公告)号：US20130082318A1

公开(公告)日：2013-04-04

申请号：US13251444

申请日：2011-10-03

申请人： Huang Liu ,  Alex Kai Hung See ,  Hai Cong ,  Zheng Zou

发明人： Huang Liu ,  Alex Kai Hung See ,  Hai Cong ,  Zheng Zou

IPC分类号： H01L29/792 ,  H01L21/762

CPC分类号： H01L21/823456 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823878 ,  H01L27/11546 ,  H01L29/66545

摘要： A memory device is fabricated through the integration of embedded non-volatile memory (eNVM) with replacement metal gate (RMG) and high-k/metal gate (HKMG) modules. Embodiments include forming two substrate portions having upper surfaces at different heights, forming non-volatile gate stacks over the substrate portion with the lower upper surface, and forming high-voltage gate stacks and logic gate stacks over the other substrate portion. Embodiments include the upper surfaces of the non-voltage gate stacks, the high-voltage gate stacks, and the logic gate stacks being substantially coplanar.

摘要翻译： 通过将嵌入式非易失性存储器（eNVM）与替代金属栅极（RMG）和高k /金属栅极（HKMG）模块集成来制造存储器件。 实施例包括形成具有不同高度的上表面的两个基板部分，在具有下上表面的基板部分上形成非易失性栅极堆叠，以及在另一个基板部分上形成高压栅极堆叠和逻辑栅极堆叠。 实施例包括非电压栅极堆叠的上表面，高压栅极堆叠以及基本共面的逻辑门叠层。

公开(公告)号：US08940637B2

公开(公告)日：2015-01-27

申请号：US13542256

申请日：2012-07-05

申请人： Lup San Leong ,  Zheng Zou ,  Alex Kai Hung See ,  Hai Cong ,  Xuesong Rao ,  Yun Ling Tan ,  Huang Liu

发明人： Lup San Leong ,  Zheng Zou ,  Alex Kai Hung See ,  Hai Cong ,  Xuesong Rao ,  Yun Ling Tan ,  Huang Liu

IPC分类号： H01L21/44 ,  H01L21/768 ,  H01L21/48

CPC分类号： H01L23/481 ,  H01L21/02107 ,  H01L21/486 ,  H01L21/76898 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13009 ,  H01L2224/1357

摘要： Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.

摘要翻译： 具有贯通硅通孔（TSV）的半导体器件不形成铜污染。 实施例包括在硅衬底中暴露围绕TSV的底部的钝化层，在暴露的钝化层上方并在硅衬底的底表面上形成硅复合层，在硅复合层上形成硬掩模层， 硅衬底的底表面，使用硬掩模层作为掩模去除围绕TSV的底部部分的硅复合层的一部分，再次暴露钝化层，以及将硬掩模层和再曝光的钝化层移除到 暴露TSV底部的触点。

公开(公告)号：US08828858B2

公开(公告)日：2014-09-09

申请号：US13353684

申请日：2012-01-19

申请人： Xuesong Rao ,  Chim Seng Seet ,  Hai Cong ,  Zheng Zou ,  Alex See ,  Yun Ling Tan ,  Wen Zhan Zhou ,  Lup San Leong

发明人： Xuesong Rao ,  Chim Seng Seet ,  Hai Cong ,  Zheng Zou ,  Alex See ,  Yun Ling Tan ,  Wen Zhan Zhou ,  Lup San Leong

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/6653 ,  H01L29/6656

摘要： Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode and substrate, the spacer layer having a first surface nearest the gate electrode and substrate, a second surface furthest from the gate electrode and substrate, and a continuously increasing etch rate from the first surface to the second surface, and etching the spacer layer to form a spacer on each side of the gate electrode. Embodiments further include forming the spacer layer by depositing a spacer material and continuously decreasing the density of the spacer material during deposition or depositing a carbon-containing spacer material and causing a gradient of carbon content in the spacer layer.

摘要翻译： 通过形成具有锥形轮廓的栅极间隔物来增强层间电介质间隙填充工艺。 实施例包括在衬底上形成栅电极，在栅电极和衬底上沉积间隔物材料，间隔层具有最靠近栅电极和衬底的第一表面，离栅电极和衬底最远的第二表面，以及连续增加 从第一表面到第二表面的蚀刻速率，并且蚀刻间隔层以在栅电极的每一侧上形成间隔物。 实施例还包括通过沉积间隔物材料形成间隔层，并在沉积期间连续降低间隔物材料的密度或沉积含碳间隔物材料并引起间隔层中的碳含量梯度。