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    SEMICONDUCTOR DEVICE WITH DOPED TRANSISTOR
    2.
    发明申请
    SEMICONDUCTOR DEVICE WITH DOPED TRANSISTOR 审中-公开
    带有DOPED晶体管的半导体器件

    公开(公告)号：US20080087958A1

    公开(公告)日：2008-04-17

    申请号：US11951833

    申请日：2007-12-06

    Applicant: Purakh Verma ,  Liang-Choo Hsia ,  Dong Kyun Sohn ,  Guowei Zhang ,  Chew Hoe Ang ,  Yun Ling Tan ,  Zhao Lun ,  Jae Gon Lee ,  Yung Fu Chong

    Inventor： Purakh Verma ,  Liang-Choo Hsia ,  Dong Kyun Sohn ,  Guowei Zhang ,  Chew Hoe Ang ,  Yun Ling Tan ,  Zhao Lun ,  Jae Gon Lee ,  Yung Fu Chong

    IPC: H01L27/088

    CPC classification number: H01L21/82385 ,  H01L21/823814 ,  H01L21/823857 ,  H01L27/11 ,  H01L29/66545 ,  H01L29/7833

    Abstract: A semiconductor device provides a substrate having a first region and a second region. A sacrificial first gate is formed in the first region. Source/drain are formed in the first region. A second region gate dielectric is formed in the second region. A second region gate is formed on the second region gate dielectric. A second region source/drain is formed in the second region. A sacrificial layer is formed over the sacrificial first gate, the source/drain, the first region, and the second region. The sacrificial first gate is exposed. A gate space is formed by removing the sacrificial first gate. A first region gate dielectric is formed in the gate space. A first region gate is formed on the first region gate dielectric. The sacrificial layer is removed.

    Abstract translation: 半导体器件提供具有第一区域和第二区域的衬底。 牺牲第一栅极形成在第一区域中。 源极/漏极形成在第一区域中。 第二区域栅极电介质形成在第二区域中。 第二区域栅极形成在第二区域栅极电介质上。 在第二区域中形成第二区域源极/漏极。 在牺牲第一栅极，源极/漏极，第一区域和第二区域上形成牺牲层。 牺牲的第一个门被暴露。 通过去除牺牲第一栅极形成栅极空间。 在栅极空间中形成第一区域栅极电介质。 第一区栅极形成在第一区栅极电介质上。 牺牲层被去除。

    SEMICONDUCTOR DEVICE AND FABRICATION METHOD
    3.
    发明申请
    SEMICONDUCTOR DEVICE AND FABRICATION METHOD 有权
    半导体器件和制造方法

    公开(公告)号：US20060252188A1

    公开(公告)日：2006-11-09

    申请号：US10908328

    申请日：2005-05-06

    Applicant: Purakh Verma ,  Liang-Choo Hsia ,  Dong Kyun Sohn ,  Guowei Zhang ,  Chew Hoe Ang ,  Yun Ling Tan ,  Zhao Lun ,  Jae Gon Lee ,  Yung Fu Chong

    Inventor： Purakh Verma ,  Liang-Choo Hsia ,  Dong Kyun Sohn ,  Guowei Zhang ,  Chew Hoe Ang ,  Yun Ling Tan ,  Zhao Lun ,  Jae Gon Lee ,  Yung Fu Chong

    IPC: H01L21/84 ,  H01L21/00

    CPC classification number: H01L21/82385 ,  H01L21/823814 ,  H01L21/823857 ,  H01L27/11 ,  H01L29/66545 ,  H01L29/7833

    Abstract: A method and apparatus for manufacturing a semiconductor device is provides a substrate having a first region and a second region. A sacrificial first gate is formed in the first region. Source/drain are formed in the first region. A second region gate dielectric is formed in the second region. A second region gate is formed on the second region gate dielectric. A second region source/drain is formed in the second region. A sacrificial layer is formed over the sacrificial first gate, the source/drain, the first region, and the second region. The sacrificial first gate is exposed. A gate space is formed by removing the sacrificial first gate. A first region gate dielectric is formed in the gate space. A first region gate is formed on the first region gate dielectric. The sacrificial layer is removed.

    Abstract translation: 用于制造半导体器件的方法和设备提供具有第一区域和第二区域的衬底。 牺牲第一栅极形成在第一区域中。 源极/漏极形成在第一区域中。 第二区域栅极电介质形成在第二区域中。 第二区域栅极形成在第二区域栅极电介质上。 在第二区域中形成第二区域源极/漏极。 在牺牲第一栅极，源极/漏极，第一区域和第二区域上形成牺牲层。 牺牲的第一个门被暴露。 通过去除牺牲第一栅极形成栅极空间。 在栅极空间中形成第一区域栅极电介质。 第一区栅极形成在第一区栅极电介质上。 牺牲层被去除。

    METHOD FOR FORMING THROUGH SILICON VIA WITH WAFER BACKSIDE PROTECTION
    4.
    发明申请
    METHOD FOR FORMING THROUGH SILICON VIA WITH WAFER BACKSIDE PROTECTION 有权
    通过硅片防止背面保护形成硅的方法

    公开(公告)号：US20140008810A1

    公开(公告)日：2014-01-09

    申请号：US13542256

    申请日：2012-07-05

    Applicant: Lup San Leong ,  Zheng Zou ,  Alex Kai Hung See ,  Hai Cong ,  Xuesong Rao ,  Yun Ling Tan ,  Huang Liu

    Inventor： Lup San Leong ,  Zheng Zou ,  Alex Kai Hung See ,  Hai Cong ,  Xuesong Rao ,  Yun Ling Tan ,  Huang Liu

    IPC: H01L21/306 ,  H01L23/48

    CPC classification number: H01L23/481 ,  H01L21/02107 ,  H01L21/486 ,  H01L21/76898 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13009 ,  H01L2224/1357

    Abstract: Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.

    Abstract translation: 具有贯通硅通孔（TSV）的半导体器件不形成铜污染。 实施例包括在硅衬底中暴露围绕TSV的底部的钝化层，在暴露的钝化层上方并在硅衬底的底表面上形成硅复合层，在硅复合层上形成硬掩模层， 硅衬底的底表面，使用硬掩模层作为掩模去除围绕TSV的底部部分的硅复合层的一部分，再次暴露钝化层，以及将硬掩模层和再曝光的钝化层移除到 暴露TSV底部的触点。

    Method and apparatus to reduce thermal variations within an integrated circuit die using thermal proximity correction
    6.
    发明授权
    Method and apparatus to reduce thermal variations within an integrated circuit die using thermal proximity correction 有权
    使用热邻近校正来减少集成电路管芯内的热变化的方法和装置

    公开(公告)号：US08293544B2

    公开(公告)日：2012-10-23

    申请号：US12220792

    申请日：2008-07-28

    Applicant: Debora Chyiu Hyia Poon ,  Alex Kh See ,  Francis Benistant ,  Benjamin Colombeau ,  Yun Ling Tan ,  Mei Sheng Zhou ,  Liang Choo Hsia

    Inventor： Debora Chyiu Hyia Poon ,  Alex Kh See ,  Francis Benistant ,  Benjamin Colombeau ,  Yun Ling Tan ,  Mei Sheng Zhou ,  Liang Choo Hsia

    IPC: H01L21/00

    CPC classification number: H01L27/088 ,  H01L27/0211

    Abstract: A method (and semiconductor device) of fabricating a semiconductor device utilizes a thermal proximity correction (TPC) technique to reduce the impact of thermal variations during anneal. Prior to actual fabrication, a location of interest (e.g., a transistor) within an integrated circuit design is determined and an effective thermal area around the location is defined. Thermal properties of structures intended to be fabricated within this area are used to calculate an estimated temperature that would be achieved at the location of interest from a given anneal process. If the estimated temperature is below or above a predetermined target temperature (or range), TPC is performed. Various TPC techniques may be performed, such as the addition of dummy cells and/or changing dimensions of the structure to be fabricated at the location of interest (resulting in an modified thermally corrected design, to suppress local variations in device performance caused by thermal variations during anneal.

    Abstract translation: 制造半导体器件的方法（和半导体器件）利用热接近校正（TPC）技术来减少退火期间热变化的影响。 在实际制造之前，确定集成电路设计中感兴趣的位置（例如，晶体管），并且定义该位置周围的有效热区。 用于在该区域内制造的结构的热性质被用于计算在给定的退火过程中在感兴趣的位置将实现的估计温度。 如果估计温度低于或高于预定目标温度（或范围），则执行TPC。 可以执行各种TPC技术，例如在感兴趣的位置添加虚拟单元和/或改变要制造的结构的尺寸（导致经修改的热校正设计，以抑制由热变化引起的器件性能的局部变化 在退火期间。

    Spacer profile engineering using films with continuously increased etch rate from inner to outer surface
    8.
    发明授权
    Spacer profile engineering using films with continuously increased etch rate from inner to outer surface 有权
    使用具有从内到外表面的不断增加的蚀刻速率的膜的间隔轮廓工程

    公开(公告)号：US08828858B2

    公开(公告)日：2014-09-09

    申请号：US13353684

    申请日：2012-01-19

    Applicant: Xuesong Rao ,  Chim Seng Seet ,  Hai Cong ,  Zheng Zou ,  Alex See ,  Yun Ling Tan ,  Wen Zhan Zhou ,  Lup San Leong

    Inventor： Xuesong Rao ,  Chim Seng Seet ,  Hai Cong ,  Zheng Zou ,  Alex See ,  Yun Ling Tan ,  Wen Zhan Zhou ,  Lup San Leong

    IPC: H01L21/3205 ,  H01L21/4763

    CPC classification number: H01L29/6653 ,  H01L29/6656

    Abstract: Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode and substrate, the spacer layer having a first surface nearest the gate electrode and substrate, a second surface furthest from the gate electrode and substrate, and a continuously increasing etch rate from the first surface to the second surface, and etching the spacer layer to form a spacer on each side of the gate electrode. Embodiments further include forming the spacer layer by depositing a spacer material and continuously decreasing the density of the spacer material during deposition or depositing a carbon-containing spacer material and causing a gradient of carbon content in the spacer layer.

    Abstract translation: 通过形成具有锥形轮廓的栅极间隔物来增强层间电介质间隙填充工艺。 实施例包括在衬底上形成栅电极，在栅电极和衬底上沉积间隔物材料，间隔层具有最靠近栅电极和衬底的第一表面，离栅电极和衬底最远的第二表面，以及连续增加 从第一表面到第二表面的蚀刻速率，并且蚀刻间隔层以在栅电极的每一侧上形成间隔物。 实施例还包括通过沉积间隔物材料形成间隔层，并在沉积期间连续降低间隔物材料的密度或沉积含碳间隔物材料并引起间隔层中的碳含量梯度。

    Step-like spacer profile
    9.
    发明授权
    Step-like spacer profile 有权
    阶梯状间隔剖面

    公开(公告)号：US08492236B1

    公开(公告)日：2013-07-23

    申请号：US13348766

    申请日：2012-01-12

    Applicant: Xuesong Rao ,  Chim Seng Seet ,  Hai Cong ,  Zheng Zou ,  Alex See ,  Yun Ling Tan ,  Wen Zhan Zhou ,  Lup San Leong ,  Huang Liu

    Inventor： Xuesong Rao ,  Chim Seng Seet ,  Hai Cong ,  Zheng Zou ,  Alex See ,  Yun Ling Tan ,  Wen Zhan Zhou ,  Lup San Leong ,  Huang Liu

    IPC: H01L21/336

    CPC classification number: H01L29/6656 ,  H01L29/78

    Abstract: Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a step-like or tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode, etching the spacer material to form a first spacer on each side of the gate electrode, and pulling back the first spacers to form second spacers which have a step-like profile. Embodiments further include depositing a second spacer material over the gate electrode and the second spacers, and etching the second spacer material to form a third spacer on each second spacer, the second and third spacers forming an outwardly tapered composite spacer.

    Abstract translation: 通过形成具有阶梯状或锥形轮廓的栅极间隔物来增强层间电介质间隙填充工艺。 实施例包括在衬底上形成栅电极，在栅电极上沉积间隔物材料，蚀刻间隔物材料以在栅电极的每一侧上形成第一间隔物，并拉回第一间隔物以形成第二间隔物， 像个人资料 实施例还包括在栅极电极和第二间隔物上沉积第二间隔物材料，并蚀刻第二间隔物材料以在每个第二间隔物上形成第三间隔物，第二和第三间隔物形成向外锥形的复合间隔物。

    SPACER PROFILE ENGINEERING USING FILMS WITH CONTINUOUSLY INCREASED ETCH RATE FROM INNER TO OUTER SURFACE
    10.
    发明申请
    SPACER PROFILE ENGINEERING USING FILMS WITH CONTINUOUSLY INCREASED ETCH RATE FROM INNER TO OUTER SURFACE 有权
    使用膜的间隙轮廓工程，从内部到外表面连续增加的刻蚀速率

    公开(公告)号：US20130187202A1

    公开(公告)日：2013-07-25

    申请号：US13353684

    申请日：2012-01-19

    Applicant: Xuesong Rao ,  Chim Seng Seet ,  Hai Cong ,  Zheng Zou ,  Alex See ,  Yun Ling Tan ,  Wen Zhan Zhou ,  Lup San Leong

    Inventor： Xuesong Rao ,  Chim Seng Seet ,  Hai Cong ,  Zheng Zou ,  Alex See ,  Yun Ling Tan ,  Wen Zhan Zhou ,  Lup San Leong

    IPC: H01L29/78 ,  H01L21/28

    CPC classification number: H01L29/6653 ,  H01L29/6656

    Abstract: Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode and substrate, the spacer layer having a first surface nearest the gate electrode and substrate, a second surface furthest from the gate electrode and substrate, and a continuously increasing etch rate from the first surface to the second surface, and etching the spacer layer to form a spacer on each side of the gate electrode. Embodiments further include forming the spacer layer by depositing a spacer material and continuously decreasing the density of the spacer material during deposition or depositing a carbon-containing spacer material and causing a gradient of carbon content in the spacer layer.

    Abstract translation: 通过形成具有锥形轮廓的栅极间隔物来增强层间电介质间隙填充工艺。 实施例包括在衬底上形成栅电极，在栅电极和衬底上沉积间隔物材料，间隔层具有最靠近栅电极和衬底的第一表面，离栅电极和衬底最远的第二表面，以及连续增加 从第一表面到第二表面的蚀刻速率，并且蚀刻间隔层以在栅电极的每一侧上形成间隔物。 实施例还包括通过沉积间隔物材料形成间隔层，并在沉积期间连续降低间隔物材料的密度或沉积含碳间隔物材料并引起间隔层中的碳含量梯度。

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