公开(公告)号：US08624329B2

公开(公告)日：2014-01-07

申请号：US12613541

申请日：2009-11-06

Applicant: Yong Meng Lee ,  Young Way Teh ,  Chung Woh Lai ,  Wenhe Lin ,  Khee Yong Lim ,  Wee Leng Tan ,  Hui Peng Koh ,  John Sudijono ,  Liang Choo Hsia

Inventor： Yong Meng Lee ,  Young Way Teh ,  Chung Woh Lai ,  Wenhe Lin ,  Khee Yong Lim ,  Wee Leng Tan ,  Hui Peng Koh ,  John Sudijono ,  Liang Choo Hsia

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L21/823864 ,  H01L21/823871 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

Abstract: A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.

Abstract translation: 第一示例性实施例提供了从栅极去除第一间隔物并将低k材料并入到ILD层中以提高器件性能的方法。 第二示例性实施例包括用低k间隔物硅化后替换第一间隔物。 这用于减小寄生电容。 此外，通过仅在硅化后实现低k间隔物，实施方案的低k间隔物不受多次高剂量离子注入和抗蚀剂剥离步骤的影响。 示例性实施例可以提高设备性能，例如边缘振荡器的性能。

公开(公告)号：US20100059831A1

公开(公告)日：2010-03-11

申请号：US12613541

申请日：2009-11-06

Applicant: Yong Meng Lee ,  Young Way Teh ,  Chung Woh Lai ,  Wenhe Lin ,  Khee Yong Lim ,  Wee Leng Tan ,  Hui Peng Koh ,  John Sudijono ,  Liang Choo Hsia

Inventor： Yong Meng Lee ,  Young Way Teh ,  Chung Woh Lai ,  Wenhe Lin ,  Khee Yong Lim ,  Wee Leng Tan ,  Hui Peng Koh ,  John Sudijono ,  Liang Choo Hsia

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/31 ,  H01L21/306

CPC classification number: H01L21/823864 ,  H01L21/823871 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

Abstract: A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.

Abstract translation: 第一示例性实施例提供了从栅极去除第一间隔物并将低k材料并入到ILD层中以提高器件性能的方法。 第二示例性实施例包括用低k间隔物硅化后替换第一间隔物。 这用于减小寄生电容。 此外，通过仅在硅化后实现低k间隔物，实施方案的低k间隔物不受多次高剂量离子注入和抗蚀剂剥离步骤的影响。 示例性实施例可以提高设备性能，例如边缘振荡器的性能。

公开(公告)号：US07445978B2

公开(公告)日：2008-11-04

申请号：US11122666

申请日：2005-05-04

Applicant: Young Way Teh ,  Yong Meng Lee ,  Chung Woh Lai ,  Wenhe Lin ,  Khee Yong Lim ,  Wee Leng Tan ,  John Sudijono ,  Hui Peng Koh ,  Liang Choo Hsia

Inventor： Young Way Teh ,  Yong Meng Lee ,  Chung Woh Lai ,  Wenhe Lin ,  Khee Yong Lim ,  Wee Leng Tan ,  John Sudijono ,  Hui Peng Koh ,  Liang Choo Hsia

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823864

Abstract: An example process to remove spacers from the gate of a NMOS transistor. A stress creating layer is formed over the NMOS and PMOS transistors and the substrate. In an embodiment, the spacers on gate are removed so that stress layer is closer to the channel of the device. The stress creating layer is preferably a tensile nitride layer. The stress creating layer is preferably a contact etch stop liner layer. In an embodiment, the gates, source and drain region have an silicide layer thereover before the stress creating layer is formed. The embodiment improves the performance of the NMOS transistors.

Abstract translation: 从NMOS晶体管的栅极去除间隔物的示例性过程。 在NMOS和PMOS晶体管和衬底上形成应力产生层。 在一个实施例中，栅极上的间隔物被去除，使得应力层更靠近器件的通道。 应力产生层优选为拉伸氮化物层。 应力产生层优选为接触蚀刻停止衬层。 在一个实施例中，栅极，源极和漏极区域在形成应力产生层之前具有硅化物层。 该实施例改善了NMOS晶体管的性能。

公开(公告)号：US20080191284A1

公开(公告)日：2008-08-14

申请号：US11672572

申请日：2007-02-08

Applicant: Christopher Vincent Baiocco ,  Xiangdong Chen ,  Wenzhi Gao ,  Young Gun Ko ,  Young Way Teh

Inventor： Christopher Vincent Baiocco ,  Xiangdong Chen ,  Wenzhi Gao ,  Young Gun Ko ,  Young Way Teh

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/31155 ,  H01L21/823864 ,  H01L29/7843 ,  Y10S438/938

Abstract: An improved method for applying stress proximity technique process on a semiconductor device and the improved device is disclosed. In one embodiment, the method utilizes an additional set of sidewall spacers on one or more NFET devices during the fabrication process. This protects the one or more of the NFET devices during the activation of a compressive PFET stress liner, thereby reducing the compressive forces on the one or more NFET devices, and creating a semiconductor device with improved performance.

Abstract translation: 公开了一种用于在半导体器件和改进的器件上应用应力接近技术工艺的改进方法。 在一个实施例中，该方法在制造过程中在一个或多个NFET器件上利用附加的一组侧壁间隔物。 这在保护压电PFET应力衬垫的激活期间保护一个或多个NFET器件，由此降低一个或多个NFET器件上的压缩力，并且产生具有改进性能的半导体器件。

公开(公告)号：US06815823B2

公开(公告)日：2004-11-09

申请号：US10679736

申请日：2003-10-06

Applicant: Young-Way Teh ,  Victor Seng Keong Lim ,  Ting Cheong Ang

Inventor： Young-Way Teh ,  Victor Seng Keong Lim ,  Ting Cheong Ang

IPC: H01L2348

CPC classification number: H01L23/5226 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76804 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A new method and structure is provided for the creation of interconnect lines. The cross section of the interconnect lines of the invention, taken in a plane that is perpendicular to the longitudinal direction of the interconnect lines, is a triangle as opposed to the conventional square or rectangular cross section of interconnect lines.

Abstract translation: 提供了一种新的方法和结构来创建互连线。 在与互连线的纵向方向垂直的平面中截取的本发明的互连线的横截面是与传统的互连线的矩形或矩形横截面相反的三角形。

公开(公告)号：US20130175617A1

公开(公告)日：2013-07-11

申请号：US13346164

申请日：2012-01-09

Applicant: Yanxiang Liu ,  Young Way Teh ,  Vara Vakada

Inventor： Yanxiang Liu ,  Young Way Teh ,  Vara Vakada

IPC: H01L29/78

CPC classification number: H01L21/823871 ,  H01L23/485 ,  H01L23/5225 ,  H01L29/1083 ,  H01L29/402 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: This application is directed to a semiconductor device with an oversized local contact as a Faraday shield, and methods of making such a semiconductor device. One illustrative device disclosed herein includes a transistor comprising a gate electrode and a source region, a source region conductor that is conductively coupled to the source region, a Faraday shield positioned above the source region conductor and the gate electrode and a first portion of a first primary metallization layer for an integrated circuit device positioned above and electrically coupled to the Faraday shield.

Abstract translation: 本申请涉及具有作为法拉第屏蔽的超大局部接触的半导体器件，以及制造这种半导体器件的方法。 本文公开的一种说明性器件包括晶体管，其包括栅极电极和源极区域，源极区域导体，其与源极区域导电耦合，位于源极区域导体和栅电极之上的法拉第屏蔽体以及第一部分 用于集成电路器件的初级金属化层，其位于法拉第屏蔽之上并电耦合到法拉第屏蔽。

公开(公告)号：US08461009B2

公开(公告)日：2013-06-11

申请号：US11307928

申请日：2006-02-28

Applicant: Atul C. Ajmera ,  Christopher V. Baiocco ,  Xiangdong Chen ,  Wenzhi Gao ,  Young Way Teh

Inventor： Atul C. Ajmera ,  Christopher V. Baiocco ,  Xiangdong Chen ,  Wenzhi Gao ,  Young Way Teh

IPC: H01L21/336

CPC classification number: H01L29/7843 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

Abstract: Process for enhancing strain in a channel with a stress liner, spacer, process for forming integrated circuit and integrated circuit. A first spacer composed of an first oxide and first nitride layer is applied to a gate electrode on a substrate, and a second spacer composed of a second oxide and second nitride layer is applied. Deep implanting of source and drain in the substrate occurs, and removal of the second nitride, second oxide, and first nitride layers.

Abstract translation: 通过应力衬垫，间隔物，集成电路形成工艺和集成电路增强通道中的应变的方法。 将由第一氧化物和第一氮化物层构成的第一间隔物施加到基板上的栅电极，并施加由第二氧化物和第二氮化物层构成的第二间隔物。 在衬底中深入植入源极和漏极，并且去除第二氮化物，第二氧化物和第一氮化物层。

公开(公告)号：US20120292719A1

公开(公告)日：2012-11-22

申请号：US13110922

申请日：2011-05-19

Applicant: Young Way TEH ,  Michael V. AQUILINO ,  Arifuzzaman (Arif) SHEIKH ,  Yun Ling TAN ,  Hao ZHANG ,  Deleep R. NAIR ,  Jinghong H. (John) LI

Inventor： Young Way TEH ,  Michael V. AQUILINO ,  Arifuzzaman (Arif) SHEIKH ,  Yun Ling TAN ,  Hao ZHANG ,  Deleep R. NAIR ,  Jinghong H. (John) LI

IPC: H01L29/772 ,  H01L21/28

CPC classification number: H01L21/28114 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/518

Abstract: A device includes a substrate with a device region surrounded by an isolation region, in which the device region includes edge portions along a width of the device region and a central portion. The device further includes a gate layer disposed on the substrate over the device region, in which the gate layer includes a graded thickness in which the gate layer at edge portions of the device region has a thickness TE that is different from a thickness TC at the central portion of the device region.

Abstract translation: 一种器件包括具有由隔离区域围绕的器件区域的衬底，其中器件区域包括沿着器件区域的宽度的边缘部分和中心部分。 该器件还包括在器件区域上设置在衬底上的栅极层，其中栅极层包括梯度厚度，其中器件区域的边缘部分处的栅极层的厚度TE不同于 设备区域的中心部分。

公开(公告)号：US20110169096A1

公开(公告)日：2011-07-14

申请号：US12687374

申请日：2010-01-14

Applicant: Xiangdong Chen ,  Weipeng Li ,  Anda C. Mocuta ,  Dae-Gyu Park ,  Melanie J. Sherony ,  Kenneth J. Stein ,  Haizhou Yin ,  Franck Arnaud ,  Jin-Ping Han ,  Laegu Kang ,  Yong Meng Lee ,  Young Way Teh ,  Voon-Yew Thean ,  Da Zhang

Inventor： Xiangdong Chen ,  Weipeng Li ,  Anda C. Mocuta ,  Dae-Gyu Park ,  Melanie J. Sherony ,  Kenneth J. Stein ,  Haizhou Yin ,  Franck Arnaud ,  Jin-Ping Han ,  Laegu Kang ,  Yong Meng Lee ,  Young Way Teh ,  Voon-Yew Thean ,  Da Zhang

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L29/7843

Abstract: An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.

Abstract translation: 集成电路结构包括衬底和衬底上或衬底中的至少一对互补晶体管。 该对互补晶体管包括第一晶体管和第二晶体管。 该结构还包括第一晶体管和第二晶体管上的第一应力产生层，以及在第一晶体管和第二晶体管上的第一应力产生层上的第二应力产生层。 第一应力产生层在第一晶体管和第二晶体管上施加拉伸应变力。 第二应力产生层对第一应力产生层，第一晶体管和第二晶体管施加压缩应变力。

公开(公告)号：US07759206B2

公开(公告)日：2010-07-20

申请号：US11164567

申请日：2005-11-29

Applicant: Zhijiong Luo ,  Young Way Teh ,  Atul C. Ajmera

Inventor： Zhijiong Luo ,  Young Way Teh ,  Atul C. Ajmera

IPC: H01L21/336

CPC classification number: H01L29/6656 ,  H01L29/6653

Abstract: A method of forming a semiconductor device that embeds an L-shaped spacer is provided. The method includes defining an L-shaped spacer on each side of a gate region of a substrate and embedding the L-shaped spacers in an oxide layer so that the oxide layer extends over a portion of the substrate a predetermined distance from a lateral edge of the L-shaped spacer. And removing oxide layers to expose the L-shape spacers.

Abstract translation: 提供一种形成嵌入L形间隔件的半导体器件的方法。 该方法包括在衬底的栅极区域的每一侧上限定L形间隔物并将L形间隔物嵌入氧化物层中，使得氧化物层在衬底的一部分上延伸超过 L形间隔物。 并且除去氧化物层以露出L形间隔物。