公开(公告)号：US08809178B2

公开(公告)日：2014-08-19

申请号：US13408139

申请日：2012-02-29

Applicant: Yanxiang Liu ,  Michael Hargrove ,  Xiaodong Yang ,  Hans van Meer ,  Laegu Kang ,  Christian Gruensfelder ,  Srikanth Samavedam

Inventor： Yanxiang Liu ,  Michael Hargrove ,  Xiaodong Yang ,  Hans van Meer ,  Laegu Kang ,  Christian Gruensfelder ,  Srikanth Samavedam

IPC: H01L21/4763

CPC classification number: H01L29/66545 ,  H01L29/66795

Abstract: One illustrative method disclosed herein includes forming a plurality of spaced-apart trenches in a semiconducting substrate to thereby define a fin structure for the device, forming a local isolation region within each of the trenches, forming a sacrificial gate structure on the fin structure, wherein the sacrificial gate structure comprises at least a sacrificial gate electrode, and forming a layer of insulating material above the fin structure and within the trench above the local isolation region. In this example, the method further includes performing at least one etching process to remove the sacrificial gate structure to thereby define a gate cavity, after removing the sacrificial gate structure, performing at least one etching process to form a recess in the local isolation region, and forming a replacement gate structure that is positioned in the recess in the local isolation region and in the gate cavity.

Abstract translation: 本文公开的一种说明性方法包括在半导体衬底中形成多个间隔开的沟槽，从而限定用于器件的鳍结构，在每个沟槽内形成局部隔离区，在翅片结构上形成牺牲栅极结构，其中 所述牺牲栅极结构至少包括牺牲栅电极，以及在所述鳍结构之上和所述局部隔离区之上的沟槽内形成绝缘材料层。 在该示例中，该方法还包括执行至少一个蚀刻工艺以去除牺牲栅极结构，从而在去除牺牲栅极结构之后，确定栅极腔，执行至少一个蚀刻工艺以在局部隔离区域中形成凹陷， 以及形成位于局部隔离区域和门腔中的凹部中的替换栅极结构。

公开(公告)号：US20130032890A1

公开(公告)日：2013-02-07

申请号：US13197631

申请日：2011-08-03

Applicant: Yanxiang Liu ,  Xiaodong Yang ,  Gan Wang

Inventor： Yanxiang Liu ,  Xiaodong Yang ,  Gan Wang

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0921

Abstract: CMOS devices (60, 61, 61′) having improved latch-up robustness are provided by including with one or both WELL regions (22, 29) underlying the source-drains (24, 25; 31, 32) and the body contacts (27, 34), one or more further regions (62, 62′, 62-2) doped with deep acceptors or deep donors (or both) of the same conductivity type as the corresponding WELL region and whose ionization substantially increases as operating temperature increases. The increase in conductivity exhibited by these further regions as a result of the increasing ionization of the deep acceptors or donors off-sets, in whole or part, the temperature driven increase in gain of the parasitic NPN and/or PNP bipolar transistors inherent in prior art CMOS structures. By clamping or lowering the gain of the parasitic bipolar transistors, the CMOS devices (60, 61, 61′) are less likely to go into latch-up with increasing operating temperature.

Abstract translation: 具有改进的闭锁稳健性的CMOS器件（60,61,61'）通过包括源极 - 漏极（24,25; 31,32）下面的一个或两个WELL区域（22,29）和主体触点 掺杂与相应的WELL区相同导电类型的深受体或深供体（或两者）的一个或多个另外的区域（62,62'，62-2），并且其电离随着工作温度的升高而显着增加 。 这些其他区域的电导率的增加是由于深受体或供体离子的电离增加导致的，全部或部分，先前的固有的寄生NPN和/或PNP双极晶体管的增益的温度驱动增加的结果 艺术CMOS结构。 通过钳位或降低寄生双极晶体管的增益，CMOS器件（60,61,61'）不太可能随着工作温度的升高而进入闭锁状态。

公开(公告)号：US20100128521A1

公开(公告)日：2010-05-27

申请号：US12275663

申请日：2008-11-21

Applicant: Yuji Mizuguchi ,  Mark W. Randolph ,  Darlene Gay Hamilton ,  Yi He ,  Zhizheng Liu ,  Yanxia (Emma) Lin ,  Xianmin Yi ,  Gulzar Kathawala ,  Amol Ramesh Joshi ,  Kuo-Tung Chang ,  Edward Franklin Runnion ,  Sung-Chul Lee ,  Sung-Yong Chung ,  Yanxiang Liu ,  Yu Sun

Inventor： Yuji Mizuguchi ,  Mark W. Randolph ,  Darlene Gay Hamilton ,  Yi He ,  Zhizheng Liu ,  Yanxia (Emma) Lin ,  Xianmin Yi ,  Gulzar Kathawala ,  Amol Ramesh Joshi ,  Kuo-Tung Chang ,  Edward Franklin Runnion ,  Sung-Chul Lee ,  Sung-Yong Chung ,  Yanxiang Liu ,  Yu Sun

IPC: G11C16/04

CPC classification number: G11C16/26 ,  G11C16/08 ,  G11C16/3427

Abstract: Systems, methods, and devices that facilitate applying a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected during a read or verify operation to facilitate reducing adjacent wordline disturb are presented. A memory component can comprise an optimized operation component that can apply a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected for a read or verify operation, based at least in part on predefined operation criteria, to facilitate reducing adjacent wordline disturb in the selected memory cell to facilitate reducing a shift in the voltage threshold and maintain a desired operation window. The optimized operation component optionally can include an evaluator component that can facilitate determining whether a negative gate voltage applied to adjacent wordlines is to be adjusted to facilitate reducing adjacent wordline disturb below a predetermined threshold amount.

Abstract translation: 提出了有助于将预定义的负栅极电压施加到与在读取或验证操作期间选择的存储器单元相关联的所选字线相邻的字线的系统，方法和设备，以便于减少相邻字线干扰。 存储器组件可以包括优化的操作部件，其可以至少部分地基于预定义的操作标准，将预定义的负栅极电压施加到与被选择用于读取或验证操作所选择的存储器单元相关联的所选字线相邻的字线上，以便减少 所选择的存储单元中的相邻字线干扰，以便减少电压阈值的移位并保持期望的操作窗口。 优化的操作组件可选地可以包括评估器组件，其可以便于确定施加到相邻字线的负栅极电压是否被调整以便于将相邻字线干扰降低到低于预定阈值量。

公开(公告)号：US08956948B2

公开(公告)日：2015-02-17

申请号：US12783914

申请日：2010-05-20

Applicant: Yanxiang Liu ,  Bin Yang

Inventor： Yanxiang Liu ,  Bin Yang

IPC: H01L21/76 ,  H01L21/762

CPC classification number: H01L21/76229 ,  H01L21/76237

Abstract: A semiconductor device is formed with extended STI regions. Embodiments include implanting oxygen under STI trenches prior to filling the trenches with oxide and subsequently annealing. An embodiment includes forming a recess in a silicon substrate, implanting oxygen into the silicon substrate below the recess, filling the recess with an oxide, and annealing the oxygen implanted silicon. The annealed oxygen implanted silicon extends the STI region, thereby reducing leakage current between N+ diffusions and N-well and between P+ diffusions and P-well, without causing STI fill holes and other defects.

Abstract translation: 半导体器件形成有延伸的STI区域。 实施例包括在用氧化物填充沟槽并随后退火之前在STI沟槽下注入氧气。 一个实施例包括在硅衬底中形成凹槽，将氧注入到凹陷下方的硅衬底中，用氧化物填充凹槽，并对氧注入的硅进行退火。 退火的氧注入硅延伸STI区域，从而减少N +扩散与N阱之间以及P +扩散与P阱之间的漏电流，而不会引起STI填充孔和其他缺陷。

公开(公告)号：US20130005103A1

公开(公告)日：2013-01-03

申请号：US13172635

申请日：2011-06-29

Applicant: Yanxiang Liu ,  Xiaodong Yang ,  Jinping Liu

Inventor： Yanxiang Liu ,  Xiaodong Yang ,  Jinping Liu

IPC: H01L21/336 ,  H01L21/28

CPC classification number: H01L21/3065 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods are provided for fabricating a FINFET integrated circuit that includes epitaxially growing a first silicon germanium layer and a second silicon layer overlying a silicon substrate. The second silicon layer is etched to form a silicon fin using the first silicon germanium layer as an etch stop. The first silicon germanium layer underlying the fin is removed to form a void underlying the fin and the void is filled with an insulating material. A gate structure is then formed overlying the fin.

Abstract translation: 提供了用于制造FINFET集成电路的方法，其包括外延生长第一硅锗层和覆盖硅衬底的第二硅层。 使用第一硅锗层作为蚀刻停止层，蚀刻第二硅层以形成硅翅片。 除去翅片下面的第一硅锗层以形成鳍片下面的空隙，并且用绝缘材料填充空隙。 然后形成覆盖鳍片的栅极结构。

公开(公告)号：US08841732B2

公开(公告)日：2014-09-23

申请号：US13197631

申请日：2011-08-03

Applicant: Yanxiang Liu ,  Xiaodong Yang ,  Gan Wang

Inventor： Yanxiang Liu ,  Xiaodong Yang ,  Gan Wang

IPC: H01L27/092

CPC classification number: H01L27/0921

Abstract: CMOS devices (60, 61, 61′) having improved latch-up robustness are provided by including with one or both WELL regions (22, 29) underlying the source-drains (24, 25; 31, 32) and the body contacts (27, 34), one or more further regions (62, 62′, 62-2) doped with deep acceptors or deep donors (or both) of the same conductivity type as the corresponding WELL region and whose ionization substantially increases as operating temperature increases. The increase in conductivity exhibited by these further regions as a result of the increasing ionization of the deep acceptors or donors off-sets, in whole or part, the temperature driven increase in gain of the parasitic NPN and/or PNP bipolar transistors inherent in prior art CMOS structures. By clamping or lowering the gain of the parasitic bipolar transistors, the CMOS devices (60, 61, 61′) are less likely to go into latch-up with increasing operating temperature.

Abstract translation: 具有改进的闭锁稳健性的CMOS器件（60,61,61'）通过包括源极 - 漏极（24,25; 31,32）下面的一个或两个WELL区域（22,29）和主体触点 掺杂与相应的WELL区相同导电类型的深受体或深供体（或两者）的一个或多个另外的区域（62,62'，62-2），并且其电离随着工作温度的升高而显着增加 。 这些其他区域的电导率的增加是由于深受体或供体的电离离子的增加，全部或部分地升高了先前的固有的寄生NPN和/或PNP双极晶体管的增益的温度驱动增加的结果 艺术CMOS结构。 通过钳位或降低寄生双极晶体管的增益，CMOS器件（60,61,61'）不太可能随着工作温度的升高而进入闭锁状态。

公开(公告)号：US08557668B2

公开(公告)日：2013-10-15

申请号：US13348771

申请日：2012-01-12

Applicant: Xiaodong Yang ,  Yanxiang Liu ,  Vara Govindeswara Reddy Vakada ,  Jinping Liu ,  Min Dai

Inventor： Xiaodong Yang ,  Yanxiang Liu ,  Vara Govindeswara Reddy Vakada ,  Jinping Liu ,  Min Dai

IPC: H01L21/336

CPC classification number: H01L29/78 ,  H01L29/6656 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/7843 ,  H01L29/7849 ,  H01L29/78654 ,  H01L29/78696

Abstract: Semiconductor devices with n-shaped bottom stress liners are formed. Embodiments include forming a protuberance on a substrate, conformally forming a sacrificial material layer over the protuberance, forming a gate stack above the sacrificial material layer on a silicon layer, removing the sacrificial material layer to form a tunnel, and forming a stress liner in the tunnel conforming to the shape of the protuberance. Embodiments further include forming a silicon layer over the sacrificial material layer and lining the tunnel with a passivation layer prior to forming the stress liner.

Abstract translation: 形成具有n形底部应力衬垫的半导体器件。 实施例包括在衬底上形成突起，在突起上保形地形成牺牲材料层，在硅层上的牺牲材料层上方形成栅极堆叠，去除牺牲材料层以形成隧道，并在其中形成应力衬垫 隧道符合突起的形状。 实施例还包括在形成应力衬垫之前在牺牲材料层上形成硅层并且在钝化层之前衬套隧道。

公开(公告)号：US20130175617A1

公开(公告)日：2013-07-11

申请号：US13346164

申请日：2012-01-09

Applicant: Yanxiang Liu ,  Young Way Teh ,  Vara Vakada

Inventor： Yanxiang Liu ,  Young Way Teh ,  Vara Vakada

IPC: H01L29/78

CPC classification number: H01L21/823871 ,  H01L23/485 ,  H01L23/5225 ,  H01L29/1083 ,  H01L29/402 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: This application is directed to a semiconductor device with an oversized local contact as a Faraday shield, and methods of making such a semiconductor device. One illustrative device disclosed herein includes a transistor comprising a gate electrode and a source region, a source region conductor that is conductively coupled to the source region, a Faraday shield positioned above the source region conductor and the gate electrode and a first portion of a first primary metallization layer for an integrated circuit device positioned above and electrically coupled to the Faraday shield.

Abstract translation: 本申请涉及具有作为法拉第屏蔽的超大局部接触的半导体器件，以及制造这种半导体器件的方法。 本文公开的一种说明性器件包括晶体管，其包括栅极电极和源极区域，源极区域导体，其与源极区域导电耦合，位于源极区域导体和栅电极之上的法拉第屏蔽体以及第一部分 用于集成电路器件的初级金属化层，其位于法拉第屏蔽之上并电耦合到法拉第屏蔽。

公开(公告)号：US20130049142A1

公开(公告)日：2013-02-28

申请号：US13218988

申请日：2011-08-26

Applicant: Yanxiang Liu ,  Jinping Liu ,  Min Dai ,  Xiaodong Yang

Inventor： Yanxiang Liu ,  Jinping Liu ,  Min Dai ,  Xiaodong Yang

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/6653 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66628

Abstract: Scaled transistors with reduced parasitic capacitance are formed by replacing a high-k dielectric sidewall spacer with a SiO2 or low-k dielectric sidewall spacer. Embodiments include transistors comprising a trench silicide layer spaced apart from a replacement metal gate electrode, and a layer of SiO2 or low-k material on a side surface of the replacement metal gate electrode facing the trench silicide layer. Implementing methodologies may include forming an intermediate structure comprising a removable gate with nitride spacers, removing the removable gate, forming a layer of high-k material on the nitride spacers, forming a layer of metal nitride on the high-k material, filling the opening with insulating material and then removing a portion thereof to form a recess, removing the metal nitride layers and layers of high-k material, depositing a layer of SiO2 or low-k material, and forming a replacement metal gate in the remaining recess.

Abstract translation: 具有减小的寄生电容的可缩放晶体管通过用SiO 2或低k电介质侧壁间隔物代替高k电介质侧壁间隔物而形成。 实施例包括晶体管，其包括与替代金属栅电极间隔开的沟槽硅化物层，以及位于替代金属栅电极的面对沟槽硅化物层的侧表面上的SiO 2或低k材料层。 实施方法可以包括形成包括具有氮化物间隔物的可移除栅极的中间结构，去除可移除栅极，在氮化物间隔物上形成高k材料层，在高k材料上形成金属氮化物层，填充开口 用绝缘材料，然后去除其一部分以形成凹槽，去除金属氮化物层和高k材料层，沉积SiO 2或低k材料层，并在剩余的凹槽中形成替换金属栅极。

公开(公告)号：US08809962B2

公开(公告)日：2014-08-19

申请号：US13218988

申请日：2011-08-26

Applicant: Yanxiang Liu ,  Jinping Liu ,  Min Dai ,  Xiaodong Yang

Inventor： Yanxiang Liu ,  Jinping Liu ,  Min Dai ,  Xiaodong Yang

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/66 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/6653 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66628

Abstract: Scaled transistors with reduced parasitic capacitance are formed by replacing a high-k dielectric sidewall spacer with a SiO2 or low-k dielectric sidewall spacer. Embodiments include transistors comprising a trench silicide layer spaced apart from a replacement metal gate electrode, and a layer of SiO2 or low-k material on a side surface of the replacement metal gate electrode facing the trench silicide layer. Implementing methodologies may include forming an intermediate structure comprising a removable gate with nitride spacers, removing the removable gate, forming a layer of high-k material on the nitride spacers, forming a layer of metal nitride on the high-k material, filling the opening with insulating material and then removing a portion thereof to form a recess, removing the metal nitride layers and layers of high-k material, depositing a layer of SiO2 or low-k material, and forming a replacement metal gate in the remaining recess.

Abstract translation: 具有减小的寄生电容的可缩放晶体管通过用SiO 2或低k电介质侧壁间隔物代替高k电介质侧壁间隔物而形成。 实施例包括晶体管，其包括与替代金属栅电极间隔开的沟槽硅化物层，以及位于替代金属栅电极的面对沟槽硅化物层的侧表面上的SiO 2或低k材料层。 实施方法可以包括形成包括具有氮化物间隔物的可移除栅极的中间结构，去除可移除栅极，在氮化物间隔物上形成高k材料层，在高k材料上形成金属氮化物层，填充开口 用绝缘材料，然后去除其一部分以形成凹槽，去除金属氮化物层和高k材料层，沉积SiO 2或低k材料层，并在剩余的凹槽中形成替换金属栅极。