公开(公告)号：US08053327B2

公开(公告)日：2011-11-08

申请号：US11614961

申请日：2006-12-21

Applicant: Shailendra Mishra ,  Lee Wee Teo ,  Yong Meng Lee ,  Zhao Lun ,  Chung Woh Lai ,  Shyue Seng Tan ,  Jeffrey Chee ,  Johnny Widodo

Inventor： Shailendra Mishra ,  Lee Wee Teo ,  Yong Meng Lee ,  Zhao Lun ,  Chung Woh Lai ,  Shyue Seng Tan ,  Jeffrey Chee ,  Johnny Widodo

IPC: H01L21/76 ,  H01L21/00

CPC classification number: H01L21/76232 ,  H01L21/76283 ,  H01L21/823481

Abstract: An integrated circuit system is provided including providing a substrate, forming an isolation structure base in the substrate without removal of the substrate, and forming a first transistor in the substrate next to the isolation structure base.

Abstract translation: 提供一种集成电路系统，包括提供衬底，在衬底中形成隔离结构基底而不去除衬底，以及在隔离结构基底旁边的衬底中形成第一晶体管。

公开(公告)号：US07999325B2

公开(公告)日：2011-08-16

申请号：US12241073

申请日：2008-09-30

Applicant: Young Way Teh ,  Yong Meng Lee ,  Chung Woh Lai ,  Wenhe Lin ,  Khee Yong Lim ,  Wee Leng Tan ,  John Sudijono ,  Hui Peng Koh ,  Liang Choo Hsia

Inventor： Young Way Teh ,  Yong Meng Lee ,  Chung Woh Lai ,  Wenhe Lin ,  Khee Yong Lim ,  Wee Leng Tan ,  John Sudijono ,  Hui Peng Koh ,  Liang Choo Hsia

IPC: H01L21/00

CPC classification number: H01L21/823807 ,  H01L21/823864

Abstract: An example process to remove spacers from the gate of a NMOS transistor. A stress creating layer is formed over the NMOS and PMOS transistors and the substrate. In an embodiment, the spacers on gate are removed so that stress layer is closer to the channel of the device. The stress creating layer is preferably a tensile nitride layer. The stress creating layer is preferably a contact etch stop liner layer. In an embodiment, the gates, source and drain region have a silicide layer thereover before the stress creating layer is formed. The embodiment improves the performance of the NMOS transistors.

Abstract translation: 从NMOS晶体管的栅极去除间隔物的示例性过程。 在NMOS和PMOS晶体管和衬底上形成应力产生层。 在一个实施例中，栅极上的间隔物被去除，使得应力层更靠近器件的通道。 应力产生层优选为拉伸氮化物层。 应力产生层优选为接触蚀刻停止衬层。 在一个实施例中，在形成应力产生层之前，栅极，源极和漏极区域之前具有硅化物层。 该实施例改善了NMOS晶体管的性能。

公开(公告)号：US07935593B2

公开(公告)日：2011-05-03

申请号：US12366356

申请日：2009-02-05

Applicant: Jong Ho Yang ,  Jin-Ping Han ,  Chung Woh Lai ,  Henry Utomo

Inventor： Jong Ho Yang ,  Jin-Ping Han ,  Chung Woh Lai ,  Henry Utomo

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

Abstract: Embodiments of the present disclosure provide stress optimization during manufacturing of dual embedded epitaxially grown (EPI) semiconductor structures using just two masks, such as nFET and pFET open for embedded epitaxial using SiC and SiGe, and separated halo implantation masks for both horizontal and vertical PC

Abstract translation: 本公开的实施例在仅使用两个掩模的双嵌入式外延生长（EPI）半导体结构的制造期间提供应力优化，例如用于使用SiC和SiGe的嵌入式外延的nFET和pFET，以及用于水平和垂直PC的分离的晕圈注入掩模

公开(公告)号：US07838372B2

公开(公告)日：2010-11-23

申请号：US12125238

申请日：2008-05-22

Applicant: Jin-Ping Han ,  Jong Ho Yang ,  Chung Woh Lai ,  Henry Utomo

Inventor： Jin-Ping Han ,  Jong Ho Yang ,  Chung Woh Lai ,  Henry Utomo

IPC: H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66636

Abstract: Methods of manufacturing semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming recesses in a first region and a second region of a workpiece. The first region of the workpiece is masked, and the recesses in the second region of the workpiece are filled with a first semiconductive material. The second region of the workpiece is masked, and the recesses in the first region of the workpiece are filled with a second semiconductive material.

Abstract translation: 公开了制造半导体器件的方法及其结构。 在一个实施例中，制造半导体器件的方法包括在工件的第一区域和第二区域中形成凹陷。 工件的第一区域被掩蔽，并且工件的第二区域中的凹部填充有第一半导体材料。 工件的第二区域被掩蔽，并且工件的第一区域中的凹部填充有第二半导体材料。

公开(公告)号：US07767577B2

公开(公告)日：2010-08-03

申请号：US12031693

申请日：2008-02-14

Applicant: Johnny Widodo ,  Liang Choo Hsia ,  James Yong Meng Lee ,  Wen Zhi Gao ,  Zhao Lun ,  Huang Liu ,  Chung Woh Lai ,  Shailendra Mishra ,  Yew Tuck Chow ,  Fang Chen ,  Shiang Yang Ong

Inventor： Johnny Widodo ,  Liang Choo Hsia ,  James Yong Meng Lee ,  Wen Zhi Gao ,  Zhao Lun ,  Huang Liu ,  Chung Woh Lai ,  Shailendra Mishra ,  Yew Tuck Chow ,  Fang Chen ,  Shiang Yang Ong

IPC: H01L21/4763 ,  H01L21/8234

CPC classification number: H01L29/41783 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823443 ,  H01L29/41725 ,  H01L29/665 ,  H01L29/7833

Abstract: A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, Rs of transistors in iso and nested regions can be matched.

Abstract translation: 在金属硅化物接触之后形成金属层，例如硅的处理层。 对硅和金属层进行退火以增加金属硅化物接触的厚度。 通过选择性地增加硅化物接触的厚度，可以匹配异和嵌套区域中的晶体管的Rs。

公开(公告)号：US20120294322A1

公开(公告)日：2012-11-22

申请号：US13565018

申请日：2012-08-02

Applicant: Chung Woh Lai ,  Xiao Hu Liu ,  Anita Madan ,  Klaus W. Schwarz ,  J. Campbell Scott

Inventor： Chung Woh Lai ,  Xiao Hu Liu ,  Anita Madan ,  Klaus W. Schwarz ,  J. Campbell Scott

IPC: H01S3/10

CPC classification number: H01L21/3221 ,  H01L21/268 ,  H01L21/2686 ,  H01L21/3226 ,  H01L29/1054 ,  H01L29/7842

Abstract: A system for manipulating dislocations on semiconductor devices, includes a moveable laser configured to generate a laser beam locally on a surface portion of the semiconductor body having a plurality of dislocations, the moveable laser being characterized as having a scan speed, the moveable laser manipulates the plurality of dislocations on the surface portion of the semiconductor body by adjusting the temperature and the scan speed of the laser beam.

Abstract translation: 一种用于操纵半导体器件上的位错的系统，包括可移动激光器，其被配置为在具有多个位错的半导体主体的表面部分局部地产生激光束，所述可移动激光器的特征在于具有扫描速度，所述可移动激光器 通过调整激光束的温度和扫描速度，半导体本体的表面部分上的多个位错。

公开(公告)号：US08178417B2

公开(公告)日：2012-05-15

申请号：US12107751

申请日：2008-04-22

Applicant: Shailendra Mishra ,  James Yong Meng Lee ,  Zhao Lun ,  Wen Zhi Gao ,  Chung Woh Lai ,  Huang Liu ,  Johnny Widodo ,  Liang Choo Hsia

Inventor： Shailendra Mishra ,  James Yong Meng Lee ,  Zhao Lun ,  Wen Zhi Gao ,  Chung Woh Lai ,  Huang Liu ,  Johnny Widodo ,  Liang Choo Hsia

IPC: H01L21/76

CPC classification number: H01L21/76229

Abstract: A method of forming shallow trench isolation (STI) structures using a multi-step etch process is disclosed. The first etch step is performed by selectively etching the substrate at a substantially higher etching rate than the mask layer to form preliminary openings having steep taper angles. The second etch step is performed by non-selectively etching the substrate to deepen the preliminary openings to form STI gaps with substantially flat bottoms.

Abstract translation: 公开了一种使用多步蚀刻工艺形成浅沟槽隔离（STI）结构的方法。 通过以比掩模层更高的蚀刻速率选择性地蚀刻衬底来进行第一蚀刻步骤，以形成具有陡峭锥角的预备开口。 第二蚀刻步骤是通过非选择性蚀刻衬底来加深初步开口以形成具有基本平坦底部的STI间隙。

公开(公告)号：US08138066B2

公开(公告)日：2012-03-20

申请号：US12242990

申请日：2008-10-01

Applicant: Chung Woh Lai ,  Xiao Hu Liu ,  Anita Madan ,  Klaus W. Schwarz ,  J. Campbell Scott

Inventor： Chung Woh Lai ,  Xiao Hu Liu ,  Anita Madan ,  Klaus W. Schwarz ,  J. Campbell Scott

IPC: H01L21/322

CPC classification number: H01L21/3221 ,  H01L21/268 ,  H01L21/2686 ,  H01L21/3226 ,  H01L29/1054 ,  H01L29/7842

Abstract: A method for generating patterned strained regions in a semiconductor device is provided. The method includes directing a light-emitting beam locally onto a surface portion of a semiconductor body; and manipulating a plurality of dislocations located proximate to the surface portion of the semiconductor body utilizing the light-emitting beam, the light-emitting beam being characterized as having a scan speed, so as to produce the patterned strained regions.

Abstract translation: 提供了一种在半导体器件中产生图案化应变区域的方法。 该方法包括将发光束局部引导到半导体本体的表面部分上; 以及利用所述发光束操作位于所述半导体主体的表面部分附近的多个位错，所述发光束的特征在于具有扫描速度，以便产生所述图案化的应变区域。

公开(公告)号：US07955936B2

公开(公告)日：2011-06-07

申请号：US12172756

申请日：2008-07-14

Applicant: Yong Siang Tan ,  Chung Woh Lai ,  Jin-Ping Han ,  Henry K. Utomo ,  Judson R. Holt ,  Eric Harley ,  Richard O. Henry ,  Richard J. Murphy

Inventor： Yong Siang Tan ,  Chung Woh Lai ,  Jin-Ping Han ,  Henry K. Utomo ,  Judson R. Holt ,  Eric Harley ,  Richard O. Henry ,  Richard J. Murphy

IPC: H01L21/336

CPC classification number: H01L29/1054 ,  H01L21/30608 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method for fabricating a semiconductor device includes forming an SiGe region. The SiGe region can be an embedded source and drain region, or a compressive SiGe channel layer, or other SiGe regions within a semiconductor device. The SiGe region is exposed to an SC1 solution and excess surface portions of the SiGe region are selectively removed. The SC1 etching process can be part of a rework method in which overgrowth regions of SiGe are selectively removed by exposing the SiGe to and SC1 solution maintained at an elevated temperature. The etching process is carried out for a period of time sufficient to remove excess surface portions of SiGe. The SC1 etching process can be carried out at elevated temperatures ranging from about 25° C. to about 65° C.

Abstract translation: 一种制造半导体器件的方法包括形成SiGe区域。 SiGe区可以是嵌入式源极和漏极区域，或者是半导体器件内的压缩SiGe沟道层或其它SiGe区域。 将SiGe区域暴露于SC1溶液，并且选择性地除去SiGe区域的多余表面部分。 SC1蚀刻工艺可以是返工方法的一部分，其中通过暴露SiGe和保持在升高的温度下的SC1溶液来选择性地除去SiGe的过度生长区域。 进行蚀刻处理足以除去SiGe的多余表面部分的一段时间。 SC1蚀刻工艺可以在约25℃至约65℃的升高的温度下进行。

公开(公告)号：US20090289379A1

公开(公告)日：2009-11-26

申请号：US12125238

申请日：2008-05-22

Applicant: Jin-Ping Han ,  Jong Ho Yang ,  Chung Woh Lai ,  Henry Utomo

Inventor： Jin-Ping Han ,  Jong Ho Yang ,  Chung Woh Lai ,  Henry Utomo

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/94 ,  H01L21/20 ,  H01L29/76 ,  H01L21/36 ,  H01L31/00

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66636

Abstract: Methods of manufacturing semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming recesses in a first region and a second region of a workpiece. The first region of the workpiece is masked, and the recesses in the second region of the workpiece are filled with a first semiconductive material. The second region of the workpiece is masked, and the recesses in the first region of the workpiece are filled with a second semiconductive material.

Abstract translation: 公开了制造半导体器件的方法及其结构。 在一个实施例中，制造半导体器件的方法包括在工件的第一区域和第二区域中形成凹陷。 工件的第一区域被掩蔽，并且工件的第二区域中的凹部填充有第一半导体材料。 工件的第二区域被掩蔽，并且工件的第一区域中的凹部填充有第二半导体材料。