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    Method to selectively form SiGe P type electrode and polysilicon N type electrode through planarization
    3.
    发明申请
    Method to selectively form SiGe P type electrode and polysilicon N type electrode through planarization 审中-公开
    通过平面化选择性地形成SiGe P型电极和多晶N型电极的方法

    公开(公告)号：US20060205138A1

    公开(公告)日：2006-09-14

    申请号：US11079731

    申请日：2005-03-14

    Applicant: Tze Chan ,  Mousumi Bhat ,  Jeffrey Chee

    Inventor： Tze Chan ,  Mousumi Bhat ,  Jeffrey Chee

    IPC: H01L21/8238

    CPC classification number: H01L21/823842 ,  H01L21/823425

    Abstract: A method for forming selective P type and N type gates is described. A first gate oxide layer is grown overlying a semiconductor substrate. A polysilicon layer is deposited overlying the first gate oxide layer. The polysilicon layer is patterned to form first NMOS gates. A second gate oxide layer is grown overlying the substrate. A polysilicon-germanium layer is deposited overlying the second gate oxide layer and the first gates. The polysilicon-germanium layer and first gates are planarized to a uniform thickness. The polysilicon first gates and the polysilicon-germanium layer are patterned to form second NMOS polysilicon gates and PMOS polysilicon-germanium gates.

    Abstract translation: 描述了形成选择性P型和N型栅极的方法。 生长在半导体衬底上的第一栅极氧化物层。 堆叠覆盖第一栅极氧化物层的多晶硅层。 图案化多晶硅层以形成第一NMOS栅极。 在衬底上生长第二栅极氧化物层。 沉积覆盖第二栅极氧化物层和第一栅极的多晶硅 - 锗层。 将多晶硅锗层和第一栅极平坦化成均匀的厚度。 图案化多晶硅第一栅极和多晶硅 - 锗层以形成第二NMOS多晶硅栅极和PMOS多晶硅 - 锗栅极。

    Capacitor top plate over source/drain to form a 1T memory device
    6.
    发明授权
    Capacitor top plate over source/drain to form a 1T memory device 有权
    源极/漏极上的电容器顶板形成1T存储器件

    公开(公告)号：US08716081B2

    公开(公告)日：2014-05-06

    申请号：US11686475

    申请日：2007-03-15

    Applicant: Lee Wee Teo ,  Yong Meng Lee ,  Zhao Lun ,  Chung Woh Lai ,  Shyue Seng Tan ,  Jeffrey Chee ,  Shailendra Mishra ,  Johnny Widodo

    Inventor： Lee Wee Teo ,  Yong Meng Lee ,  Zhao Lun ,  Chung Woh Lai ,  Shyue Seng Tan ,  Jeffrey Chee ,  Shailendra Mishra ,  Johnny Widodo

    IPC: H01L29/76

    CPC classification number: H01L29/94 ,  H01L27/10805 ,  H01L27/1085 ,  H01L27/11

    Abstract: A method and structure for a memory device, such as a 1T-SRAM, having a capacitor top plate directly over a doped bottom plate region. An example device comprises the following. An isolation film formed as to surround an active area on a substrate. A gate dielectric and gate electrode formed over a portion of the active area. A source element and a drain element in the substrate adjacent to the gate electrode. The drain element is comprised of a drain region and a bottom plate region. The drain region is between the bottom plate region and the gate structure. A capacitor dielectric and a capacitor top plate are over at least portions of the bottom plate region.

    Abstract translation: 用于诸如1T-SRAM的存储器件的方法和结构，其具有直接在掺杂底板区域上方的电容器顶板。 示例设备包括以下。 形成为围绕衬底上的有源区域的隔离膜。 形成在有源区域的一部分上的栅极电介质和栅电极。 与栅电极相邻的衬底中的源极元件和漏极元件。 漏极元件由漏区和底板区组成。 漏极区域位于底板区域和栅极结构之间。 电容器电介质和电容器顶板在底板区域的至少部分上方。

    Method to selectively form poly SiGe P type electrode and polysilicon N type electrode through planarization
    7.
    发明授权
    Method to selectively form poly SiGe P type electrode and polysilicon N type electrode through planarization 失效
    通过平面化选择性地形成多晶SiGe P型电极和多晶N型电极的方法

    公开(公告)号：US06872608B1

    公开(公告)日：2005-03-29

    申请号：US10697746

    申请日：2003-10-30

    Applicant: Tze Ho Chan ,  Mousumi Bhat ,  Jeffrey Chee

    Inventor： Tze Ho Chan ,  Mousumi Bhat ,  Jeffrey Chee

    IPC: H01L21/28 ,  H01L21/8238 ,  H01L21/338 ,  H01L21/00 ,  H01L21/84

    CPC classification number: H01L21/823842 ,  H01L21/2807

    Abstract: A method for forming selective P type and N type gates is described. A first gate oxide layer is grown overlying a semiconductor substrate. A polysilicon layer is deposited overlying the first gate oxide layer. The polysilicon layer is patterned to form first NMOS gates. A second gate oxide layer is grown overlying the substrate. A polysilicon-germanium layer is deposited overlying the second gate oxide layer and the first gates. The polysilicon-germanium layer and first gates are planarized to a uniform thickness. The polysilicon first gates and the polysilicon-germanium layer are patterned to form second NMOS polysilicon gates and PMOS polysilicon-germanium gates.

    Abstract translation: 描述了形成选择性P型和N型栅极的方法。 生长在半导体衬底上的第一栅极氧化物层。 堆叠覆盖第一栅极氧化物层的多晶硅层。 图案化多晶硅层以形成第一NMOS栅极。 在衬底上生长第二栅极氧化物层。 沉积覆盖第二栅极氧化物层和第一栅极的多晶硅 - 锗层。 将多晶硅锗层和第一栅极平坦化成均匀的厚度。 图案化多晶硅第一栅极和多晶硅 - 锗层以形成第二NMOS多晶硅栅极和PMOS多晶硅 - 锗栅极。

    Dual Si-Ge polysilicon gate with different Ge concentrations for CMOS device optimization
    8.
    发明授权
    Dual Si-Ge polysilicon gate with different Ge concentrations for CMOS device optimization 失效
    具有不同Ge浓度的双Si-Ge多晶硅栅极用于CMOS器件优化

    公开(公告)号：US06709912B1

    公开(公告)日：2004-03-23

    申请号：US10266425

    申请日：2002-10-08

    Applicant: Chew-Hoe Ang ,  Jeffrey Chee Wei-Lun ,  Wenhe Lin ,  Jia Zhen Zheng

    Inventor： Chew-Hoe Ang ,  Jeffrey Chee Wei-Lun ,  Wenhe Lin ,  Jia Zhen Zheng

    IPC: H01L218238

    CPC classification number: H01L21/823842 ,  Y10S438/933

    Abstract: A method for forming a dual Si—Ge poly-gates having different Ge concentrations is described. An NMOS active area and a PMOS active area are provided on a semiconductor substrate separated by an isolation region. A gate oxide layer is grown overlying the semiconductor substrate in each of the active areas. A polycrystalline silicon-germanium (Si—Ge) layer is deposited overlying the gate oxide layer wherein the polycrystalline Si—Ge layer has a first Ge concentration. The NMOS active area is blocked while the PMOS active area is exposed. Successive cycles of Ge plasma doping and laser annealing into the PMOS active area are performed to achieve a second Ge concentration higher than the first Ge concentration. The polycrystalline Si—Ge layer is patterned to form a gate in each of the active areas wherein the gate in the PMOS active area has a higher Ge concentration than the gate in the NMOS active area to complete formation of dual Si—Ge polysilicon gates with different Ge concentrations in the fabrication of an integrated circuit device.

    Abstract translation: 描述了形成具有不同Ge浓度的双Si-Ge多栅极的方法。 在由隔离区隔开的半导体衬底上提供NMOS有源区和PMOS有源区。 生长在每个有源区域中的半导体衬底上的栅氧化层。 沉积在多晶Si-Ge层具有第一Ge浓度的栅极氧化物层上的多晶硅 - 锗（Si-Ge）层。 当PMOS有源区域暴露时，NMOS有源区域被阻塞。 进行Ge等离子体掺杂和激光退火到PMOS有源区的连续循环以实现高于第一Ge浓度的第二Ge浓度。 多晶Si-Ge层被图案化以在每个有源区域中形成栅极，其中PMOS有源区中的栅极具有比NMOS有源区域中的栅极更高的Ge浓度，以完成双Si-Ge多晶硅栅极的形成， 在集成电路器件的制造中不同的Ge浓度。

    Method to lower work function of gate electrode through Ge implantation
    10.
    发明授权
    Method to lower work function of gate electrode through Ge implantation 有权
    通过Ge注入来降低栅电极的功函数的方法

    公开(公告)号：US07101746B2

    公开(公告)日：2006-09-05

    申请号：US10701963

    申请日：2003-11-05

    Applicant: Tze Ho Simon Chan ,  Mousumi Bhat ,  Jeffrey Chee

    Inventor： Tze Ho Simon Chan ,  Mousumi Bhat ,  Jeffrey Chee

    IPC: H01L21/8238 ,  H01L21/336

    CPC classification number: H01L21/823842 ,  H01L21/32155 ,  H01L21/82385

    Abstract: A method for forming selective P type and N type gates is described. A gate oxide layer is grown overlying a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. Germanium ions are implanted into a portion of the polysilicon layer not covered by a mask to form a polysilicon-germanium layer. The polysilicon layer and the polysilicon-germanium layer are patterned to form NMOS polysilicon gates and PMOS polysilicon-germanium gates. In an alternative, nitrogen ions are implanted into the polysilicon-germanium layer and the gates are annealed after patterning to redistribute the germanium ions throughout the polysilicon-germanium layer. In a second alternative, germanium ions are implanted into a first thin polysilicon layer, then a second polysilicon layer is deposited to achieve the total polysilicon layer thickness before patterning the gates.

    Abstract translation: 描述了形成选择性P型和N型栅极的方法。 生长在半导体衬底上的栅氧化层。 沉积在栅极氧化物层上的多晶硅层。 将锗离子注入到未被掩模覆盖的多晶硅层的一部分中以形成多晶硅 - 锗层。 图案化多晶硅层和多晶硅 - 锗层以形成NMOS多晶硅栅极和PMOS多晶硅 - 锗栅极。 替代地，将氮离子注入到多晶硅 - 锗层中，并且在图案化之后对栅极进行退火以将锗离子重新分布在整个多晶硅 - 锗层中。 在第二替代方案中，将锗离子注入到第一薄多晶硅层中，然后沉积第二多晶硅层以在栅极图案化之前实现总多晶硅层厚度。

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