Invention Grant
US06872608B1 Method to selectively form poly SiGe P type electrode and polysilicon N type electrode through planarization
失效
通过平面化选择性地形成多晶SiGe P型电极和多晶N型电极的方法
- Patent Title: Method to selectively form poly SiGe P type electrode and polysilicon N type electrode through planarization
- Patent Title (中): 通过平面化选择性地形成多晶SiGe P型电极和多晶N型电极的方法
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Application No.: US10697746Application Date: 2003-10-30
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Publication No.: US06872608B1Publication Date: 2005-03-29
- Inventor: Tze Ho Chan , Mousumi Bhat , Jeffrey Chee
- Applicant: Tze Ho Chan , Mousumi Bhat , Jeffrey Chee
- Applicant Address: SG Singapore
- Assignee: Chartered Semiconductor Manufacturing Ltd.
- Current Assignee: Chartered Semiconductor Manufacturing Ltd.
- Current Assignee Address: SG Singapore
- Agent George O. Saile; Rosemary L. S. Pike
- Main IPC: H01L21/28
- IPC: H01L21/28 ; H01L21/8238 ; H01L21/338 ; H01L21/00 ; H01L21/84
Abstract:
A method for forming selective P type and N type gates is described. A first gate oxide layer is grown overlying a semiconductor substrate. A polysilicon layer is deposited overlying the first gate oxide layer. The polysilicon layer is patterned to form first NMOS gates. A second gate oxide layer is grown overlying the substrate. A polysilicon-germanium layer is deposited overlying the second gate oxide layer and the first gates. The polysilicon-germanium layer and first gates are planarized to a uniform thickness. The polysilicon first gates and the polysilicon-germanium layer are patterned to form second NMOS polysilicon gates and PMOS polysilicon-germanium gates.
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