公开(公告)号：US20060205138A1

公开(公告)日：2006-09-14

申请号：US11079731

申请日：2005-03-14

Applicant: Tze Chan ,  Mousumi Bhat ,  Jeffrey Chee

Inventor： Tze Chan ,  Mousumi Bhat ,  Jeffrey Chee

IPC: H01L21/8238

CPC classification number: H01L21/823842 ,  H01L21/823425

Abstract: A method for forming selective P type and N type gates is described. A first gate oxide layer is grown overlying a semiconductor substrate. A polysilicon layer is deposited overlying the first gate oxide layer. The polysilicon layer is patterned to form first NMOS gates. A second gate oxide layer is grown overlying the substrate. A polysilicon-germanium layer is deposited overlying the second gate oxide layer and the first gates. The polysilicon-germanium layer and first gates are planarized to a uniform thickness. The polysilicon first gates and the polysilicon-germanium layer are patterned to form second NMOS polysilicon gates and PMOS polysilicon-germanium gates.

Abstract translation: 描述了形成选择性P型和N型栅极的方法。 生长在半导体衬底上的第一栅极氧化物层。 堆叠覆盖第一栅极氧化物层的多晶硅层。 图案化多晶硅层以形成第一NMOS栅极。 在衬底上生长第二栅极氧化物层。 沉积覆盖第二栅极氧化物层和第一栅极的多晶硅 - 锗层。 将多晶硅锗层和第一栅极平坦化成均匀的厚度。 图案化多晶硅第一栅极和多晶硅 - 锗层以形成第二NMOS多晶硅栅极和PMOS多晶硅 - 锗栅极。

公开(公告)号：US20050158956A1

公开(公告)日：2005-07-21

申请号：US10759671

申请日：2004-01-16

Applicant: Chyiu Poon ,  Leng Tan ,  Byung Cho ,  Alex See ,  Mousumi Bhat

Inventor： Chyiu Poon ,  Leng Tan ,  Byung Cho ,  Alex See ,  Mousumi Bhat

IPC: H01L21/265 ,  H01L21/268 ,  H01L21/324 ,  H01L21/8238 ,  H01L21/336

CPC classification number: H01L21/268 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/823418

Abstract: A process is described to form a semiconductor device such as MOSFET or CMOS with shallow junctions in the source/drain extension regions. After forming the shallow trench isolations and the gate stack, sidewall dielectric spacers are removed. A pre-amorphizing implant (PAI) is performed with Ge+ or Si+ ions to form a thin PAI layer on the surface of the silicon regions adjacent to the gate stack. B+ ion implantation is then performed to form source/drain extension (SDE) regions. The B+ implant step is then followed by multiple-pulsed 248 nm KrF excimer laser anneal with pulse duration of 23 ns. This step is to reduce the sheet resistance of the junction through the activation of the boron dopant in the SDE junctions. Laser anneal is then followed by rapid thermal anneal (RTA) to repair the residual damage and also to induce out-diffusion of the boron to yield shallower junctions than the just-implanted junctions prior to RTA.

Abstract translation: 描述了一种工艺以在源极/漏极延伸区域中形成具有浅结的诸如MOSFET或CMOS的半导体器件。 在形成浅沟槽隔离物和栅极堆叠之后，去除侧壁电介质间隔物。 用Ge + +或Si + +离子进行预非晶化植入物（PAI），以在邻近栅叠层的硅区域的表面上形成薄的PAI层。 然后进行离子注入以形成源极/漏极延伸（SDE）区域。 然后，B + / /> /注入步骤之后是脉冲持续时间为23ns的多脉冲248nm KrF准分子激光退火。 该步骤是通过SDE结中的硼掺杂剂的激活来降低结的薄层电阻。 然后激光退火之后是快速热退火（RTA），以修复残余损伤，并且还引起硼的扩散，从而产生比RTA之前刚刚植入的结更浅的结。

公开(公告)号：US07101746B2

公开(公告)日：2006-09-05

申请号：US10701963

申请日：2003-11-05

Applicant: Tze Ho Simon Chan ,  Mousumi Bhat ,  Jeffrey Chee

Inventor： Tze Ho Simon Chan ,  Mousumi Bhat ,  Jeffrey Chee

IPC: H01L21/8238 ,  H01L21/336

CPC classification number: H01L21/823842 ,  H01L21/32155 ,  H01L21/82385

Abstract: A method for forming selective P type and N type gates is described. A gate oxide layer is grown overlying a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. Germanium ions are implanted into a portion of the polysilicon layer not covered by a mask to form a polysilicon-germanium layer. The polysilicon layer and the polysilicon-germanium layer are patterned to form NMOS polysilicon gates and PMOS polysilicon-germanium gates. In an alternative, nitrogen ions are implanted into the polysilicon-germanium layer and the gates are annealed after patterning to redistribute the germanium ions throughout the polysilicon-germanium layer. In a second alternative, germanium ions are implanted into a first thin polysilicon layer, then a second polysilicon layer is deposited to achieve the total polysilicon layer thickness before patterning the gates.

Abstract translation: 描述了形成选择性P型和N型栅极的方法。 生长在半导体衬底上的栅氧化层。 沉积在栅极氧化物层上的多晶硅层。 将锗离子注入到未被掩模覆盖的多晶硅层的一部分中以形成多晶硅 - 锗层。 图案化多晶硅层和多晶硅 - 锗层以形成NMOS多晶硅栅极和PMOS多晶硅 - 锗栅极。 替代地，将氮离子注入到多晶硅 - 锗层中，并且在图案化之后对栅极进行退火以将锗离子重新分布在整个多晶硅 - 锗层中。 在第二替代方案中，将锗离子注入到第一薄多晶硅层中，然后沉积第二多晶硅层以在栅极图案化之前实现总多晶硅层厚度。

公开(公告)号：US06291888B1

公开(公告)日：2001-09-18

申请号：US09461251

申请日：1999-12-15

Applicant: Mousumi Bhat ,  Mark D. Hall ,  Arkalgud R. Sitaram ,  Michael P. Woo

Inventor： Mousumi Bhat ,  Mark D. Hall ,  Arkalgud R. Sitaram ,  Michael P. Woo

IPC: H01L214763

CPC classification number: H01L21/76805 ,  H01L21/76831 ,  H01L21/76895

Abstract: Electrical shorts and leakage paths are virtually eliminated by recessing conductive nodules (52) away from a conductor (72) or not forming the conductive nodules at all. In one embodiment, the refractory metal containing material (52) is recessed from the edge of the opening (32). When forming a nitride layer (54) within the opening (32), conductive nodules (52) are formed from a portion of the refractory metal containing material (20) such that the conductive nodules (52) lie within the recession (42). In another embodiment, an oxide layer (82, 102) is formed adjacent to the refractory metal containing material (20) before forming a nitride layer (84, 112).

Abstract translation: 实际上通过使导电结节（52）远离导体（72）凹陷或完全不形成导电结节来消除电短路和漏电路径。 在一个实施例中，含难熔金属材料（52）从开口（32）的边缘凹进。 当在开口（32）内形成氮化物层（54）时，导电结核（52）由含难熔金属材料（20）的一部分形成，使得导电结核（52）位于凹陷（42）内。 在另一个实施例中，在形成氮化物层（84,112）之前，邻近难熔金属材料（20）形成氧化物层（82,102）。

公开(公告)号：US5515319A

公开(公告)日：1996-05-07

申请号：US135935

申请日：1993-10-12

Applicant: Michael C. Smayling ,  Iano D'Arrigo ,  Giovanni Santin ,  Georges Falessi ,  Mousumi Bhat

Inventor： Michael C. Smayling ,  Iano D'Arrigo ,  Giovanni Santin ,  Georges Falessi ,  Mousumi Bhat

IPC: G11C16/10 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  G11C7/00

CPC classification number: H01L27/11526 ,  G11C16/10 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11546 ,  H01L29/7885

Abstract: A non-volatile memory cell 10 is disclosed herein. The cell is formed in a first semiconductor region 12 of a first conductivity type. A second semiconductor region 14 of a second conductivity type formed over the first semiconductor region 12. A third semiconductor region 16 of the first conductivity type formed over the second semiconductor region 14. In the preferred embodiment, the second and third regions 14 and 16 are well regions formed within the first region 12. Other regions such as epitaxially grown layers can also be used. First and second source/drain regions 18 and 20 are formed within the third semiconductor region 16. These second source/drain regions 18 and 20 are separated by a channel region 22. A floating gate 26 overlies at least a portion of the channel region 22 while a control gate 30 overlies the floating gate 26.

Abstract translation: 本文公开了非易失性存储单元10。 电池形成在第一导电类型的第一半导体区域12中。 形成在第一半导体区域12上的第二导电类型的第二半导体区域14.在第二半导体区域14上形成的第一导电类型的第三半导体区域16.在优选实施例中，第二和第三区域14和16是 形成在第一区域12内的阱区。也可以使用其它区域，例如外延生长层。 第一和第二源极/漏极区域18和20形成在第三半导体区域16内。这些第二源极/漏极区域18和20被沟道区域22分开。浮置栅极26覆盖沟道区域22的至少一部分 而控制门30覆盖浮动门26。

公开(公告)号：US5349225A

公开(公告)日：1994-09-20

申请号：US46571

申请日：1993-04-12

Applicant: Donald J. Redwine ,  Mousumi Bhat ,  Michael Smayling

Inventor： Donald J. Redwine ,  Mousumi Bhat ,  Michael Smayling

IPC: H01L21/336 ,  H01L29/08 ,  H01L29/78 ,  H01L29/06 ,  H01L21/268

CPC classification number: H01L29/0847 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7836

Abstract: A transistor device 10 formed in a semiconductor layer 12 is disclosed herein. A first source/drain region 14 is formed in the semiconductor layer 12. A second source/drain region 16 is also formed in the semiconductor layer 12 and is spaced from the first source/drain region 14 by a channel region 18. The second source/drain region 16 includes (1) a lightly doped portion 16b adjacent the channel region 18 and abutting the top surface, (2) a main portion 16a abutting the top surface and spaced from the channel region 18 by the lightly doped portion 16b, and (3) a deep portion 16c formed within the layer 12 and spaced from the top surface by the lightly doped portion 16b and the main portion 16a. A gate electrode 20 is formed over at least a portion of the channel region 18 and insulated therefrom.

Abstract translation: 本文公开了形成在半导体层12中的晶体管器件10。 第一源极/漏极区域14形成在半导体层12中。第二源极/漏极区域16也形成在半导体层12中并且通过沟道区域18与第一源极/漏极区域14间隔开。第二源极 漏极区域16包括：（1）与沟道区域18相邻的轻微掺杂部分16b并邻接顶部表面;（2）与顶部表面邻接的主要部分16a，并且通过轻掺杂部分16b与沟道区域18隔开;以及 （3）形成在层12内并且由轻掺杂部分16b和主要部分16a与顶表面隔开的深部分16c。 栅电极20形成在通道区域18的至少一部分上并与其绝缘。

公开(公告)号：US06897118B1

公开(公告)日：2005-05-24

申请号：US10776794

申请日：2004-02-11

Applicant: Chyiu-Hyia Poon ,  Byung Jin Cho ,  Yong Feng Lu ,  Alex See ,  Mousumi Bhat

Inventor： Chyiu-Hyia Poon ,  Byung Jin Cho ,  Yong Feng Lu ,  Alex See ,  Mousumi Bhat

IPC: H01L21/265 ,  H01L21/268 ,  H01L21/324 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/20 ,  H01L21/36

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L21/324 ,  H01L21/823814

Abstract: A method for forming a highly activated ultra shallow ion implanted semiconductive elements for use in sub-tenth micron MOSFET technology is described. A key feature of the method is the ability to activate the implanted impurity to a highly active state without permitting the dopant to diffuse further to deepen the junction. A selected single crystalline silicon active region is first amorphized by implanting a heavy ion such as silicon or germanium. A semiconductive impurity for example boron is then implanted and activated by pulsed laser annealing whereby the pulse fluence, frequency, and duration are chosen to maintain the amorphized region just below it's melting temperature. It is found that just below the melting temperature there is sufficient local ion mobility to secure the dopant into active positions within the silicon matrix to achieve a high degree of activation with essentially no change in concentration profile. The selection of the proper laser annealing parameters is optimized by observation of the reduction of sheet resistance and concentration profile as measured on a test site. Application of the method is applied to forming a MOS FET and a CMOS device. The additional processing steps required by the invention are applied simultaneously to both n-channel and p-channel devices of the CMOS device pair.

Abstract translation: 描述了用于形成用于次十分之一米MOSFET技术的高激活超浅离子注入半导体元件的方法。 该方法的关键特征是能够将注入的杂质激活到高活性状态，而不允许掺杂剂进一步扩散以加深该结。 选择的单晶硅有源区域首先通过注入重离子如硅或锗来非晶化。 然后通过脉冲激光退火将诸如硼的半导体杂质注入并激活，由此选择脉冲能量密度，频率和持续时间以将非晶化区域保持在低于其熔融温度。 已经发现，恰好低于熔融温度，存在足够的局部离子迁移率，以将掺杂剂固定在硅基质内的活性位置，以实现高度的活化，基本上没有浓度分布的变化。 通过观察在测试部位测量的薄层电阻和浓度分布的降低来优化选择适当的激光退火参数。 该方法的应用用于形成MOS FET和CMOS器件。 本发明所需的附加处理步骤同时应用于CMOS器件对的n沟道和p沟道器件。

公开(公告)号：US20050095773A1

公开(公告)日：2005-05-05

申请号：US10701963

申请日：2003-11-05

Applicant: Tze Ho Chan ,  Mousumi Bhat ,  Jeffrey Chee

Inventor： Tze Ho Chan ,  Mousumi Bhat ,  Jeffrey Chee

IPC: H01L21/3215 ,  H01L21/8238 ,  H01R4/64 ,  H01L21/302 ,  H01L21/461 ,  H01R4/60

CPC classification number: H01L21/823842 ,  H01L21/32155 ,  H01L21/82385

Abstract: A method for forming selective P type and N type gates is described. A gate oxide layer is grown overlying a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. Germanium ions are implanted into a portion of the polysilicon layer not covered by a mask to form a polysilicon-germanium layer. The polysilicon layer and the polysilicon-germanium layer are patterned to form NMOS polysilicon gates and PMOS polysilicon-germanium gates. In an alternative, nitrogen ions are implanted into the polysilicon-germanium layer and the gates are annealed after patterning to redistribute the germanium ions throughout the polysilicon-germanium layer. In a second alternative, germanium ions are implanted into a first thin polysilicon layer, then a second polysilicon layer is deposited to achieve the total polysilicon layer thickness before patterning the gates.

Abstract translation: 描述了形成选择性P型和N型栅极的方法。 生长在半导体衬底上的栅氧化层。 沉积在栅极氧化物层上的多晶硅层。 将锗离子注入到未被掩模覆盖的多晶硅层的一部分中以形成多晶硅 - 锗层。 图案化多晶硅层和多晶硅 - 锗层以形成NMOS多晶硅栅极和PMOS多晶硅 - 锗栅极。 替代地，将氮离子注入到多晶硅 - 锗层中，并且在图案化之后对栅极进行退火以将锗离子重新分布在整个多晶硅 - 锗层中。 在第二替代方案中，将锗离子注入到第一薄多晶硅层中，然后沉积第二多晶硅层以在栅极图案化之前实现总多晶硅层厚度。

公开(公告)号：US07112499B2

公开(公告)日：2006-09-26

申请号：US10759671

申请日：2004-01-16

Applicant: Chyiu Hyia Poon ,  Leng Seow Tan ,  Byung Jin Cho ,  Alex See ,  Mousumi Bhat

Inventor： Chyiu Hyia Poon ,  Leng Seow Tan ,  Byung Jin Cho ,  Alex See ,  Mousumi Bhat

IPC: H01L21/336 ,  H01L21/31 ,  H01L21/469

CPC classification number: H01L21/268 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/823418

Abstract: A process is described to form a semiconductor device such as MOSFET or CMOS with shallow junctions in the source/drain extension regions. After forming the shallow trench isolations and the gate stack, sidewall dielectric spacers are removed. A pre-amorphizing implant (PAI) is performed with Ge+ or Si+ ions to form a thin PAI layer on the surface of the silicon regions adjacent to the gate stack. B+ ion implantation is then performed to form source/drain extension (SDE) regions. The B+ implant step is then followed by multiple-pulsed 248 nm KrF excimer laser anneal with pulse duration of 23 ns. This step is to reduce the sheet resistance of the junction through the activation of the boron dopant in the SDE junctions. Laser anneal is then followed by rapid thermal anneal (RTA) to repair the residual damage and also to induce out-diffusion of the boron to yield shallower junctions than the just-implanted junctions prior to RTA.

Abstract translation: 描述了一种工艺以在源极/漏极延伸区域中形成具有浅结的诸如MOSFET或CMOS的半导体器件。 在形成浅沟槽隔离物和栅极堆叠之后，去除侧壁电介质间隔物。 用Ge + +或Si + +离子进行预非晶化植入物（PAI），以在邻近栅叠层的硅区域的表面上形成薄的PAI层。 然后进行离子注入以形成源极/漏极延伸（SDE）区域。 然后，B + / /> /注入步骤之后是脉冲持续时间为23ns的多脉冲248nm KrF准分子激光退火。 该步骤是通过SDE结中的硼掺杂剂的激活来降低结的薄层电阻。 然后激光退火之后是快速热退火（RTA）以修复残余损伤，并且还引起硼的扩散，从而产生比RTA之前刚刚植入的结更浅的结。

公开(公告)号：US06872608B1

公开(公告)日：2005-03-29

申请号：US10697746

申请日：2003-10-30

Applicant: Tze Ho Chan ,  Mousumi Bhat ,  Jeffrey Chee

Inventor： Tze Ho Chan ,  Mousumi Bhat ,  Jeffrey Chee

IPC: H01L21/28 ,  H01L21/8238 ,  H01L21/338 ,  H01L21/00 ,  H01L21/84

CPC classification number: H01L21/823842 ,  H01L21/2807

Abstract: A method for forming selective P type and N type gates is described. A first gate oxide layer is grown overlying a semiconductor substrate. A polysilicon layer is deposited overlying the first gate oxide layer. The polysilicon layer is patterned to form first NMOS gates. A second gate oxide layer is grown overlying the substrate. A polysilicon-germanium layer is deposited overlying the second gate oxide layer and the first gates. The polysilicon-germanium layer and first gates are planarized to a uniform thickness. The polysilicon first gates and the polysilicon-germanium layer are patterned to form second NMOS polysilicon gates and PMOS polysilicon-germanium gates.

Abstract translation: 描述了形成选择性P型和N型栅极的方法。 生长在半导体衬底上的第一栅极氧化物层。 堆叠覆盖第一栅极氧化物层的多晶硅层。 图案化多晶硅层以形成第一NMOS栅极。 在衬底上生长第二栅极氧化物层。 沉积覆盖第二栅极氧化物层和第一栅极的多晶硅 - 锗层。 将多晶硅锗层和第一栅极平坦化成均匀的厚度。 图案化多晶硅第一栅极和多晶硅 - 锗层以形成第二NMOS多晶硅栅极和PMOS多晶硅 - 锗栅极。