公开(公告)号：US08178417B2

公开(公告)日：2012-05-15

申请号：US12107751

申请日：2008-04-22

Applicant: Shailendra Mishra ,  James Yong Meng Lee ,  Zhao Lun ,  Wen Zhi Gao ,  Chung Woh Lai ,  Huang Liu ,  Johnny Widodo ,  Liang Choo Hsia

Inventor： Shailendra Mishra ,  James Yong Meng Lee ,  Zhao Lun ,  Wen Zhi Gao ,  Chung Woh Lai ,  Huang Liu ,  Johnny Widodo ,  Liang Choo Hsia

IPC: H01L21/76

CPC classification number: H01L21/76229

Abstract: A method of forming shallow trench isolation (STI) structures using a multi-step etch process is disclosed. The first etch step is performed by selectively etching the substrate at a substantially higher etching rate than the mask layer to form preliminary openings having steep taper angles. The second etch step is performed by non-selectively etching the substrate to deepen the preliminary openings to form STI gaps with substantially flat bottoms.

Abstract translation: 公开了一种使用多步蚀刻工艺形成浅沟槽隔离（STI）结构的方法。 通过以比掩模层更高的蚀刻速率选择性地蚀刻衬底来进行第一蚀刻步骤，以形成具有陡峭锥角的预备开口。 第二蚀刻步骤是通过非选择性蚀刻衬底来加深初步开口以形成具有基本平坦底部的STI间隙。

公开(公告)号：US07767577B2

公开(公告)日：2010-08-03

申请号：US12031693

申请日：2008-02-14

Applicant: Johnny Widodo ,  Liang Choo Hsia ,  James Yong Meng Lee ,  Wen Zhi Gao ,  Zhao Lun ,  Huang Liu ,  Chung Woh Lai ,  Shailendra Mishra ,  Yew Tuck Chow ,  Fang Chen ,  Shiang Yang Ong

Inventor： Johnny Widodo ,  Liang Choo Hsia ,  James Yong Meng Lee ,  Wen Zhi Gao ,  Zhao Lun ,  Huang Liu ,  Chung Woh Lai ,  Shailendra Mishra ,  Yew Tuck Chow ,  Fang Chen ,  Shiang Yang Ong

IPC: H01L21/4763 ,  H01L21/8234

CPC classification number: H01L29/41783 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823443 ,  H01L29/41725 ,  H01L29/665 ,  H01L29/7833

Abstract: A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, Rs of transistors in iso and nested regions can be matched.

Abstract translation: 在金属硅化物接触之后形成金属层，例如硅的处理层。 对硅和金属层进行退火以增加金属硅化物接触的厚度。 通过选择性地增加硅化物接触的厚度，可以匹配异和嵌套区域中的晶体管的Rs。

公开(公告)号：US08143651B2

公开(公告)日：2012-03-27

申请号：US12848999

申请日：2010-08-02

Applicant: Johnny Widodo ,  Liang Choo Hsia ,  James Yong Meng Lee ,  Wen Zhi Gao ,  Zhao Lun ,  Huang Liu ,  Chung Woh Lai ,  Shailendra Mishra ,  Yew Tuck Chow ,  Fang Chen ,  Shiang Yang Ong

Inventor： Johnny Widodo ,  Liang Choo Hsia ,  James Yong Meng Lee ,  Wen Zhi Gao ,  Zhao Lun ,  Huang Liu ,  Chung Woh Lai ,  Shailendra Mishra ,  Yew Tuck Chow ,  Fang Chen ,  Shiang Yang Ong

IPC: H01L27/10 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/41783 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823443 ,  H01L29/41725 ,  H01L29/665 ,  H01L29/7833

Abstract: A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, Rs of transistors in iso and nested regions can be matched.

Abstract translation: 在金属硅化物接触之后形成金属层，例如硅的处理层。 对硅和金属层进行退火以增加金属硅化物接触的厚度。 通过选择性地增加硅化物接触的厚度，可以匹配异和嵌套区域中的晶体管的Rs。

公开(公告)号：US20100301424A1

公开(公告)日：2010-12-02

申请号：US12848999

申请日：2010-08-02

Applicant: Johnny WIDODO ,  Liang Choo HSIA ,  James Yong Meng LEE ,  Wen Zhi GAO ,  Zhao LUN ,  Huang LIU ,  Chung Woh LAI ,  Shailendra MISHRA ,  Yew Tuck CHOW ,  Fang CHEN ,  Shiang Yang ONG

Inventor： Johnny WIDODO ,  Liang Choo HSIA ,  James Yong Meng LEE ,  Wen Zhi GAO ,  Zhao LUN ,  Huang LIU ,  Chung Woh LAI ,  Shailendra MISHRA ,  Yew Tuck CHOW ,  Fang CHEN ,  Shiang Yang ONG

IPC: H01L29/78

CPC classification number: H01L29/41783 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823443 ,  H01L29/41725 ,  H01L29/665 ,  H01L29/7833

Abstract: A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, Rs of transistors in iso and nested regions can be matched.

Abstract translation: 在金属硅化物接触之后形成金属层，例如硅的处理层。 对硅和金属层进行退火以增加金属硅化物接触的厚度。 通过选择性地增加硅化物接触的厚度，可以匹配异和嵌套区域中的晶体管的Rs。

公开(公告)号：US20090261448A1

公开(公告)日：2009-10-22

申请号：US12107751

申请日：2008-04-22

Applicant: Shailendra MISHRA ,  James Yong Meng LEE ,  Zhao LUN ,  Wen Zhi GAO ,  Chung Woh LAI ,  Huang LIU ,  Johnny WIDODO ,  Liang Choo HSIA

Inventor： Shailendra MISHRA ,  James Yong Meng LEE ,  Zhao LUN ,  Wen Zhi GAO ,  Chung Woh LAI ,  Huang LIU ,  Johnny WIDODO ,  Liang Choo HSIA

IPC: H01L21/762 ,  H01L23/58

CPC classification number: H01L21/76229

Abstract: A method of forming shallow trench isolation (STI) structures using a multi-step etch process is disclosed. The first etch step is performed by selectively etching the substrate at a substantially higher etching rate than the mask layer to form preliminary openings having steep taper angles. The second etch step is performed by non-selectively etching the substrate to deepen the preliminary openings to form STI gaps with substantially flat bottoms.

Abstract translation: 公开了一种使用多步蚀刻工艺形成浅沟槽隔离（STI）结构的方法。 通过以比掩模层更高的蚀刻速率选择性地蚀刻衬底来进行第一蚀刻步骤，以形成具有陡峭锥角的预备开口。 第二蚀刻步骤是通过非选择性蚀刻衬底来加深初步开口以形成具有基本平坦底部的STI间隙。

公开(公告)号：US20090206408A1

公开(公告)日：2009-08-20

申请号：US12031693

申请日：2008-02-14

Applicant: Johnny WIDODO ,  Liang Choo HSIA ,  James Yong Meng LEE ,  Wen Zhi GAO ,  Zhao LUN ,  Huang LIU ,  Chung Woh LAI ,  Shailendra MISHRA ,  Yew Tuck CHOW ,  Fang CHEN ,  Shiang Yang ONG

Inventor： Johnny WIDODO ,  Liang Choo HSIA ,  James Yong Meng LEE ,  Wen Zhi GAO ,  Zhao LUN ,  Huang LIU ,  Chung Woh LAI ,  Shailendra MISHRA ,  Yew Tuck CHOW ,  Fang CHEN ,  Shiang Yang ONG

IPC: H01L29/00 ,  H01L21/44

CPC classification number: H01L29/41783 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823443 ,  H01L29/41725 ,  H01L29/665 ,  H01L29/7833

Abstract: A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, Rs of transistors in iso and nested regions can be matched.

Abstract translation: 在金属硅化物接触之后形成金属层，例如硅的处理层。 对硅和金属层进行退火以增加金属硅化物接触的厚度。 通过选择性地增加硅化物接触的厚度，可以匹配异和嵌套区域中的晶体管的Rs。