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    SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME
    1.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20160300949A1

    公开(公告)日：2016-10-13

    申请号：US15062553

    申请日：2016-03-07

    Applicant: Tae-Jong LEE ,  Sanghyuk HONG ,  TaeYong KWON ,  Sunjung KIM ,  Cheol KIM

    Inventor： Tae-Jong LEE ,  Sanghyuk HONG ,  TaeYong KWON ,  Sunjung KIM ,  Cheol KIM

    IPC: H01L29/78 ,  H01L29/161 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/66 ,  H01L29/08 ,  H01L29/16

    Abstract: Semiconductor devices and methods of fabricating the same are provided. The methods of fabricating the semiconductor devices may include providing a substrate including an active pattern protruding from the substrate, forming a first liner layer and a field isolating pattern on the substrate to cover a lower portion of the active pattern, forming a second liner layer on an upper portion of the active pattern and the field isolation pattern, and forming a dummy gate on the second liner layer.

    Abstract translation: 提供半导体器件及其制造方法。 制造半导体器件的方法可以包括提供包括从衬底突出的有源图案的衬底，在衬底上形成第一衬里层和场隔离图案以覆盖有源图案的下部，形成第二衬垫层 有源图案的上部和场隔离图案，并且在第二衬垫层上形成伪栅极。

    Method for fabricating complementary silicon on insulator devices using wafer bonding
    6.
    发明授权
    Method for fabricating complementary silicon on insulator devices using wafer bonding 失效
    使用晶片接合制造绝缘体上互补硅的方法

    公开(公告)号：US06468880B1

    公开(公告)日：2002-10-22

    申请号：US09805954

    申请日：2001-03-15

    Applicant: Yeow Kheng Lim ,  Randall Cher Liang Cha ,  Alex See ,  Tae Jong Lee ,  Wang Ling Goh

    Inventor： Yeow Kheng Lim ,  Randall Cher Liang Cha ,  Alex See ,  Tae Jong Lee ,  Wang Ling Goh

    IPC: H01L2130

    CPC classification number: H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  Y10S438/977

    Abstract: A method to form a silicon on insulator (SOI) device using wafer bonding. A first substrate is provided having an insulating layer over a first side. A second substrate is provided having first isolation regions (e.g., STI) that fill first trenches in the second substrate. Next, we bond the first and second substrate together by bonding the insulating layer to the first isolation regions and the second substrate. Then, a stop layer is formed over the second side of the second substrate. The stop layer and the second side of the second substrate are patterned to form second trenches in the second substrate. The second trenches have sidewalls at least partially defined by the isolation regions and the second trenches expose the second insulating layer. The second trenches define first active regions over the first isolation regions (STI) and define second active regions over the insulating layer. Next, the second trenches are filled with an insulator material to from second isolation regions. Next, the stop layer is removed. Lastly, devices are formed in and on the active regions.

    Abstract translation: 一种使用晶片接合形成绝缘体上硅（SOI）器件的方法。 提供第一基板，其在第一侧上具有绝缘层。 提供了第二衬底，其具有填充第二衬底中的第一沟槽的第一隔离区域（例如STI）。 接下来，通过将绝缘层粘合到第一隔离区域和第二基板上，将第一和第二基板结合在一起。 然后，在第二基板的第二侧上形成止挡层。 图案化第二基板的阻挡层和第二侧，以在第二基板中形成第二沟槽。 第二沟槽具有由隔离区域至少部分地限定的侧壁，并且第二沟槽露出第二绝缘层。 第二沟槽限定第一隔离区域（STI）上的第一有源区，并在绝缘层上限定第二有源区。 接下来，第二沟槽用绝缘体材料填充到第二隔离区域。 接下来，停止层被去除。 最后，在活动区域​​中形成器件。

    Simplified method to reduce or eliminate STI oxide divots
    7.
    发明授权
    Simplified method to reduce or eliminate STI oxide divots 失效
    简化方法来减少或消除STI氧化层

    公开(公告)号：US06432797B1

    公开(公告)日：2002-08-13

    申请号：US09768487

    申请日：2001-01-25

    Applicant: Randall Cher Liang Cha ,  Tae Jong Lee ,  Alex See ,  Lap Chan ,  Yeow Kheng Lim

    Inventor： Randall Cher Liang Cha ,  Tae Jong Lee ,  Alex See ,  Lap Chan ,  Yeow Kheng Lim

    IPC: H01L2176

    CPC classification number: H01L21/76237 ,  H01L21/31053 ,  H01L21/31055

    Abstract: A method for forming shallow trench isolation wherein oxide divots at the edge of the isolation and active regions are reduced or eliminated is described. A trench is etched into a semiconductor substrate. An oxide layer is deposited overlying the semiconductor substrate and filling the trench. Nitrogen atoms are implanted into the oxide layer overlying the trench. The substrate is annealed whereby a layer of nitrogen-rich oxide is formed at the surface of the oxide layer overlying the trench. The oxide layer is planarized to the semiconductor substrate wherein the nitrogen-rich oxide layer is planarized more slowly than the oxide layer resulting in a portion of the oxide layer remaining overlying the trench after the oxide layer overlying the semiconductor substrate has been removed wherein the portion of the oxide layer remaining provides a smooth transition between the shallow trench isolation and the active areas completing the formation of shallow trench isolation in the fabrication of an integrated circuit device.

    Abstract translation: 描述了形成浅沟槽隔离的方法，其中在隔离和有源区的边缘处的氧化物凹陷被减少或消除。 将沟槽蚀刻到半导体衬底中。 沉积在半导体衬底上并填充沟槽的氧化物层。 将氮原子注入到覆盖沟槽的氧化物层中。 将衬底退火，由此在覆盖沟槽的氧化物层的表面上形成一层富氮氧化物。 氧化物层平坦化到半导体衬底，其中富氧氧化物层平坦化比氧化物层缓慢，导致一部分氧化物层保留在沟槽上方，在氧化物层覆盖半导体衬底之后，其中部分 剩余的氧化物层在浅沟槽隔离和有源区域之间提供平滑的过渡，从而在集成电路器件的制造中完成浅沟槽隔离的形成。

    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
    8.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20160307927A1

    公开(公告)日：2016-10-20

    申请号：US14993212

    申请日：2016-01-12

    Applicant: Jung-Han Lee ,  Jae-Hwan Lee ,  Sang-Su Kim ,  Hwan-Wook Choi ,  Tae-Jong Lee ,  Seung-Mo Ha

    Inventor： Jung-Han Lee ,  Jae-Hwan Lee ,  Sang-Su Kim ,  Hwan-Wook Choi ,  Tae-Jong Lee ,  Seung-Mo Ha

    IPC: H01L27/12 ,  H01L29/06 ,  H01L27/088

    CPC classification number: H01L29/0657 ,  H01L21/823431 ,  H01L21/823468 ,  H01L27/0886

    Abstract: A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.

    Abstract translation: 半导体器件包括由衬底上的隔离层限定的多个有源散热片，活性散热片上的栅极结构和隔离层，以及覆盖栅极结构的侧壁的栅极间隔结构。 栅极结构的侧壁分别包括具有第一，第二和第三斜率的第一，第二和第三区域。 第二斜坡从底部向第二区域的顶部增加。 第二斜坡在第二区域的底部具有小于第一斜坡的值。 第三斜率大于第二斜率。

    Circuit Module and Battery Pack Including the Same
    9.
    发明申请
    Circuit Module and Battery Pack Including the Same 有权
    电路模块和电池组包括它

    公开(公告)号：US20120262123A1

    公开(公告)日：2012-10-18

    申请号：US13335875

    申请日：2011-12-22

    Applicant: Tae-Jong Lee ,  Ben Lim

    Inventor： Tae-Jong Lee ,  Ben Lim

    IPC: H02J7/00 ,  G01R1/20

    CPC classification number: G01R1/20 ,  G01R31/3606 ,  H01C3/12 ,  H02J7/007

    Abstract: A circuit module of a battery pack includes a pattern resistor having conductivity; a temperature sensor that is adjacent to the pattern resistor and that senses a temperature of the pattern resistor; and a current detecting unit that is electrically connected to both ends of the pattern resistor, that is electrically connected to the temperature sensor, and that detects a current flowing in the pattern resistor based on a voltage across the ends of the pattern resistor and a temperature of the pattern resistor.

    Abstract translation: 电池组的电路模块包括具有导电性的图案电阻器; 温度传感器，其与图案电阻器相邻并且感测图案电阻器的温度; 以及电流检测单元，其电连接到图案电阻器的两端，其电连接到温度传感器，并且基于图案电阻器两端的电压检测在图案电阻器中流动的电流，并且温度 的图案电阻。

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