公开(公告)号：US10219492B2

公开(公告)日：2019-03-05

申请号：US14550399

申请日：2014-11-21

Applicant: Xiaoyong Bao ,  Yong Sun Lee

Inventor： Xiaoyong Bao ,  Yong Sun Lee

IPC: A61K31/70 ,  C12N15/63 ,  A01K67/027 ,  A61K31/713 ,  A61K45/06 ,  C12N15/113 ,  A01K67/00

Abstract: Provided herein are methods for altering respiratory syncytial virus (RSV) replication in a cell using oligonucleotides derived from tRNAs, also referred to as tRFs (tRNA-derived RNA Fragments). The oligonucleotides may be used to decrease or increase replication of RSV. Also provided herein are methods for treating a subject having or at risk of having an RSV infection, and animal models for evaluating viral and host factors in RSV pathogenesis.

公开(公告)号：US07592227B2

公开(公告)日：2009-09-22

申请号：US11481928

申请日：2006-07-07

Applicant: Yong-Sun Lee ,  Jai-Dong Lee ,  Bong-Hyun Kim ,  Man-Sug Kang ,  Jung-Hwan Kim ,  Hyun-Jin Shin ,  Won-Seok Yoo ,  Seung-Mok Shin

Inventor： Yong-Sun Lee ,  Jai-Dong Lee ,  Bong-Hyun Kim ,  Man-Sug Kang ,  Jung-Hwan Kim ,  Hyun-Jin Shin ,  Won-Seok Yoo ,  Seung-Mok Shin

IPC: H01L21/336

CPC classification number: H01L21/32105 ,  H01L21/28273 ,  H01L29/42324

Abstract: Example embodiments of the present invention relate to methods of manufacturing a semiconductor device. Other example embodiments of the present invention relate to methods of manufacturing a semiconductor device having a gate electrode. In the method of manufacturing the semiconductor device, a gate electrode may be formed on a semiconductor substrate. Damage in the semiconductor substrate and a sidewall of the gate electrode may be cured, or repaired, by a radical re-oxidation process to form an oxide layer on the semiconductor substrate and the gate electrode. The radical re-oxidation process may be performed by providing a nitrogen gas onto the semiconductor substrate while increasing a temperature of the semiconductor substrate to a first temperature to passivate a surface of the gate electrode under a nitrogen gas atmosphere, providing an oxygen gas onto the semiconductor substrate while increasing the temperature from a first temperature to a second temperature to perform a first oxidation process and/or performing a second oxidation process at the second temperature.

Abstract translation: 本发明的示例性实施例涉及制造半导体器件的方法。 本发明的其它示例实施例涉及制造具有栅电极的半导体器件的方法。 在制造半导体器件的方法中，可以在半导体衬底上形成栅电极。 可以通过自由基再氧化工艺固化或修复半导体衬底和栅电极的侧壁的损伤，以在半导体衬底和栅电极上形成氧化物层。 可以通过在半导体衬底上提供氮气同时将半导体衬底的温度提高到第一温度以在氮气气氛下钝化栅电极的表面来进行自由基再氧化工艺，从而将氧气提供到 半导体衬底，同时将温度从第一温度升至第二温度，以进行第一氧化工艺和/或在第二温度下进行第二氧化工艺。

公开(公告)号：US07375391B2

公开(公告)日：2008-05-20

申请号：US11246590

申请日：2005-10-11

Applicant: Jung-Ho Moon ,  Jae-Min Yu ,  Don-Woo Lee ,  Chul-Soon Kwon ,  In-Gu Yoon ,  Yong-Sun Lee ,  Jae-Hyun Park

Inventor： Jung-Ho Moon ,  Jae-Min Yu ,  Don-Woo Lee ,  Chul-Soon Kwon ,  In-Gu Yoon ,  Yong-Sun Lee ,  Jae-Hyun Park

IPC: H01L29/76 ,  H01L29/788 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11539

Abstract: A semiconductor device includes a substrate divided into a memory cell region and a logic region. A split gate electrode structure is formed in a memory cell region of a substrate. A silicon oxide layer is formed on a sidewall of the split gate electrode structure and a surface of the substrate. A word line is formed on the silicon oxide layer that is positioned on the sidewall of the split gate electrode structure. The word line has an upper width and a lower width. The lower width is greater than the upper width. A logic gate pattern is formed on a logic region of the substrate. The logic gate pattern has a thickness thinner than the lower width of the word line.

Abstract translation: 半导体器件包括分为存储单元区域和逻辑区域的衬底。 在基板的存储单元区域中形成分割栅电极结构。 在分离栅电极结构的侧壁和基板的表面上形成氧化硅层。 在位于分离栅电极结构的侧壁上的氧化硅层上形成字线。 字线具有上宽度和下宽度。 较低的宽度大于上部宽度。 在基板的逻辑区域上形成逻辑门图案。 逻辑门图案具有比字线的较低宽度更薄的厚度。

公开(公告)号：US07205194B2

公开(公告)日：2007-04-17

申请号：US10874579

申请日：2004-06-24

Applicant: Yong-Sun Lee ,  Jae-Min Yu ,  Don-Woo Lee ,  Jung-Hun Cho ,  Chul-Soon Kwon ,  Jung-Ho Moon ,  In-Gu Yoon ,  Jae-Hyun Park

Inventor： Yong-Sun Lee ,  Jae-Min Yu ,  Don-Woo Lee ,  Jung-Hun Cho ,  Chul-Soon Kwon ,  Jung-Ho Moon ,  In-Gu Yoon ,  Jae-Hyun Park

IPC: H01L21/336

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

Abstract: A method of fabricating a flash memory cell having a split gate structure. A sacrificial layer is formed on a floating gate layer formed on a semiconductor substrate. The sacrificial layer is etched to form an opening exposing a portion of the floating gate layer. A gate interlayer insulating layer pattern is formed inside the opening. After removing the sacrificial layer pattern and etching the floating gate layer (using the gate interlayer insulating layer pattern as an etch mask), a floating gate is formed under the gate interlayer insulating layer pattern. A control gate is formed overlapping a portion of the floating gate.

Abstract translation: 一种制造具有分裂栅极结构的闪存单元的方法。 牺牲层形成在形成在半导体衬底上的浮栅上。 牺牲层被蚀刻以形成暴露浮动栅极层的一部分的开口。 在开口内部形成栅极层间绝缘层图案。 在去除牺牲层图案并蚀刻浮栅（使用栅极层间绝缘层图案作为蚀刻掩模）之后，在栅极层间绝缘层图案下方形成浮栅。 控制栅极形成为与浮置栅极的一部分重叠。

公开(公告)号：US20060027858A1

公开(公告)日：2006-02-09

申请号：US11246590

申请日：2005-10-11

Applicant: Jung-Ho Moon ,  Jae-Min Yu ,  Don-Woo Lee ,  Chul-Soon Kwon ,  In-Gu Yoon ,  Yong-Sun Lee ,  Jae-Hyun Park

Inventor： Jung-Ho Moon ,  Jae-Min Yu ,  Don-Woo Lee ,  Chul-Soon Kwon ,  In-Gu Yoon ,  Yong-Sun Lee ,  Jae-Hyun Park

IPC: H01L29/788

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11539

Abstract: A semiconductor device includes a substrate divided into a memory cell region and a logic region. A split gate electrode structure is formed in a memory cell region of a substrate. A silicon oxide layer is formed on a sidewall of the split gate electrode structure and a surface of the substrate. A word line is formed on the silicon oxide layer that is positioned on the sidewall of the split gate electrode structure. The word line has an upper width and a lower width. The lower width is greater than the upper width. A logic gate pattern is formed on a logic region of the substrate. The logic gate pattern has a thickness thinner than the lower width of the word line.

Abstract translation: 半导体器件包括分为存储单元区域和逻辑区域的衬底。 在基板的存储单元区域中形成分割栅电极结构。 在分离栅电极结构的侧壁和基板的表面上形成氧化硅层。 在位于分离栅电极结构的侧壁上的氧化硅层上形成字线。 字线具有上宽度和下宽度。 较低的宽度大于上部宽度。 在基板的逻辑区域上形成逻辑门图案。 逻辑门图案具有比字线的较低宽度更薄的厚度。

公开(公告)号：US20050063208A1

公开(公告)日：2005-03-24

申请号：US10840803

申请日：2004-05-07

Applicant: Jae-Hyun Park ,  Jae-Min Yu ,  Chul-Soon Kwon ,  In-gu Yoon ,  Eung-yung Ahn ,  Jung-ho Moon ,  Yong-Sun Lee ,  Sung-Yung Jeon

Inventor： Jae-Hyun Park ,  Jae-Min Yu ,  Chul-Soon Kwon ,  In-gu Yoon ,  Eung-yung Ahn ,  Jung-ho Moon ,  Yong-Sun Lee ,  Sung-Yung Jeon

IPC: H01L21/8247 ,  G11C11/42 ,  G11C16/04 ,  H01L21/28 ,  H01L21/336 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/66825 ,  G11C16/0425 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7885

Abstract: There is provided a method of fabricating a split-gate flash memory cell using a spacer oxidation process. An oxidation barrier layer is formed on a floating gate layer, and an opening to expose a portion of the floating gate layer is formed in the oxidation barrier layer. Subsequently, a spacer is formed on a sidewall of the opening with a material layer having insulation property by oxidizing, and an inter-gate oxide layer pattern between a floating gate and a control gate is formed in the opening while the spacer is oxidized by performing an oxidation process.

Abstract translation: 提供了使用间隔物氧化工艺制造分裂栅极闪存单元的方法。 在浮栅层上形成氧化阻挡层，在氧化阻挡层中形成露出浮栅的一部分的开口。 随后，通过氧化形成具有绝缘性的材料层的开口的侧壁上的间隔物，并且在开口中形成浮栅和控制栅之间的栅间氧化层图案，同时通过执行 氧化过程。

公开(公告)号：US20100307788A1

公开(公告)日：2010-12-09

申请号：US12867074

申请日：2008-06-26

Applicant: Ung Kim ,  Hwa-Joon Lim ,  Yong-Sun Lee ,  Jin-Ho Nam

Inventor： Ung Kim ,  Hwa-Joon Lim ,  Yong-Sun Lee ,  Jin-Ho Nam

IPC: H01B9/02 ,  H01B1/24

CPC classification number: C08K5/20 ,  C08K3/04 ,  C08K5/54

Abstract: The present invention relates to a peelable and water-crosslinked semiconductive resin composition. The peelable and water-crosslinked semiconductive resin composition includes 100 parts by weight of a basic resin; 20 to 80 parts by weight of carbon black based on weight of the basic resin; and 0.05 to 5.0 parts by weight of an amide-based lubricant based on weight of the basic resin, wherein the basic resin is a mixed resin including 60 to 80 weight % of an ethylene-based copolymer resin that is bonded with an unsaturated organic silane and has a melting point of 80° C. or above; 5 to 20 weight % of an ethylene-acrylic acid copolymer or its alkali metal salt; and 5 to 40 parts by weight of an ethylene propylene copolymer containing 5 to 20 weight % of ethylene, or a propylene rein.

Abstract translation: 本发明涉及一种可剥离和水交联的半导体树脂组合物。 可剥离和水交联的半导体树脂组合物包括100重量份的碱性树脂; 20〜80重量份基于树脂重量的炭黑; 和0.05-5.0重量份基于碱性树脂重量的酰胺类润滑剂，其中所述碱性树脂是包含60-80重量％的与不饱和有机硅烷键合的乙烯类共聚物树脂的混合树脂 并具有80℃以上的熔点; 5〜20重量％的乙烯 - 丙烯酸共聚物或其碱金属盐; 和5至40重量份的含有5至20重量％乙烯或丙烯的乙烯丙烯共聚物。

公开(公告)号：US20070010068A1

公开(公告)日：2007-01-11

申请号：US11481928

申请日：2006-07-07

Applicant: Yong-Sun Lee ,  Jai-Dong Lee ,  Bong-Hyun Kim ,  Man-Sug Kang ,  Jung-Hwan Kim ,  Hyun-Jin Shin ,  Won-Seok Yoo ,  Seung-Mok Shin

Inventor： Yong-Sun Lee ,  Jai-Dong Lee ,  Bong-Hyun Kim ,  Man-Sug Kang ,  Jung-Hwan Kim ,  Hyun-Jin Shin ,  Won-Seok Yoo ,  Seung-Mok Shin

IPC: H01L21/30 ,  H01L21/46

CPC classification number: H01L21/32105 ,  H01L21/28273 ,  H01L29/42324

Abstract: Example embodiments of the present invention relate to methods of manufacturing a semiconductor device. Other example embodiments of the present invention relate to methods of manufacturing a semiconductor device having a gate electrode. In the method of manufacturing the semiconductor device, a gate electrode may be formed on a semiconductor substrate. Damage in the semiconductor substrate and a sidewall of the gate electrode may be cured, or repaired, by a radical re-oxidation process to form an oxide layer on the semiconductor substrate and the gate electrode. The radical re-oxidation process may be performed by providing a nitrogen gas onto the semiconductor substrate while increasing a temperature of the semiconductor substrate to a first temperature to passivate a surface of the gate electrode under a nitrogen gas atmosphere, providing an oxygen gas onto the semiconductor substrate while increasing the temperature from a first temperature to a second temperature to perform a first oxidation process and/or performing a second oxidation process at the second temperature.

Abstract translation: 本发明的示例性实施例涉及制造半导体器件的方法。 本发明的其它示例实施例涉及制造具有栅电极的半导体器件的方法。 在制造半导体器件的方法中，可以在半导体衬底上形成栅电极。 可以通过自由基再氧化工艺固化或修复半导体衬底和栅电极的侧壁的损伤，以在半导体衬底和栅电极上形成氧化物层。 可以通过在半导体衬底上提供氮气同时将半导体衬底的温度提高到第一温度以在氮气气氛下钝化栅电极的表面来进行自由基再氧化工艺，从而将氧气提供到 半导体衬底，同时将温度从第一温度升至第二温度，以进行第一氧化工艺和/或在第二温度下进行第二氧化工艺。

公开(公告)号：US20050064661A1

公开(公告)日：2005-03-24

申请号：US10874579

申请日：2004-06-24

Applicant: Yong-Sun Lee ,  Jae-Min Yu ,  Don-Woo Lee ,  Jung-Hun Cho ,  Chul-Soon Kwon ,  Jung-Ho Moon ,  In-Gu Yoon ,  Jae-Hyun Park

Inventor： Yong-Sun Lee ,  Jae-Min Yu ,  Don-Woo Lee ,  Jung-Hun Cho ,  Chul-Soon Kwon ,  Jung-Ho Moon ,  In-Gu Yoon ,  Jae-Hyun Park

IPC: H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

Abstract: A method of fabricating a flash memory cell having a split gate structure. A sacrificial layer is formed on a floating gate layer formed on a semiconductor substrate. The sacrificial layer is etched to form an opening exposing a portion of the floating gate layer. A gate interlayer insulating layer pattern is formed inside the opening. After removing the sacrificial layer pattern and etching the floating gate layer (using the gate interlayer insulating layer pattern as an etch mask), a floating gate is formed under the gate interlayer insulating layer pattern. A control gate is formed overlapping a portion of the floating gate.

Abstract translation: 一种制造具有分裂栅极结构的闪存单元的方法。 牺牲层形成在形成在半导体衬底上的浮栅上。 牺牲层被蚀刻以形成暴露浮动栅极层的一部分的开口。 在开口内部形成栅极层间绝缘层图案。 在去除牺牲层图案并蚀刻浮栅（使用栅极层间绝缘层图案作为蚀刻掩模）之后，在栅极层间绝缘层图案下方形成浮栅。 控制栅极形成为与浮置栅极的一部分重叠。

公开(公告)号：US20150152420A1

公开(公告)日：2015-06-04

申请号：US14550399

申请日：2014-11-21

Applicant: XIAOYONG BAO ,  YONG SUN LEE

Inventor： XIAOYONG BAO ,  YONG SUN LEE

IPC: C12N15/113 ,  A61K45/06 ,  A01K67/027 ,  A61K31/713

CPC classification number: A01K67/0271 ,  A61K31/713 ,  A61K45/06 ,  C12N15/113 ,  C12N2310/11 ,  C12N2310/315 ,  C12N2310/321 ,  C12N2760/18511 ,  C12N2310/3521

Abstract: Provided herein are methods for altering respiratory syncytial virus (RSV) replication in a cell using oligonucleotides derived from tRNAs, also referred to as tRFs (tRNA-derived RNA Fragments). The oligonucleotides may be used to decrease or increase replication of RSV. Also provided herein are methods for treating a subject having or at risk of having an RSV infection, and animal models for evaluating viral and host factors in RSV pathogenesis.

Abstract translation: 本文提供了使用衍生自tRNA（也称为tRNA衍生的RNA片段）的寡核苷酸改变细胞中呼吸道合胞病毒（RSV）复制的方法。 寡核苷酸可用于降低或增加RSV的复制。 本文还提供了治疗患有RSV感染或具有RSV感染风险的受试者的方法，以及用于评估RSV发病机理中的病毒和宿主因子的动物模型。