公开(公告)号：US09490165B2

公开(公告)日：2016-11-08

申请号：US12982862

申请日：2010-12-30

Applicant: Luying Du ,  Fan Zhang ,  Jun Chen ,  Bei Chao Zhang ,  Juan Boon Tan

Inventor： Luying Du ,  Fan Zhang ,  Jun Chen ,  Bei Chao Zhang ,  Juan Boon Tan

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76835 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments relate to a method for forming reliable interconnects by preparing a substrate with a dielectric layer, processing the dielectric layer to serve as an IMD layer, wherein the IMD layer comprises a hybrid IMD layer comprising a plurality of dielectric materials with different k values.

Abstract translation: 实施例涉及通过制备具有电介质层的衬底来形成可靠互连的方法，处理介电层以用作IMD层，其中IMD层包括具有不同k值的多个介电材料的混合IMD层。

公开(公告)号：US20140035155A1

公开(公告)日：2014-02-06

申请号：US13565748

申请日：2012-08-02

Applicant: Juan Boon TAN ,  Yeow Kheng LIM ,  Soh Yun SIAH ,  Wei LIU ,  Shunqiang GONG

Inventor： Juan Boon TAN ,  Yeow Kheng LIM ,  Soh Yun SIAH ,  Wei LIU ,  Shunqiang GONG

IPC: H01L23/48 ,  H01L21/50 ,  H01L21/768

CPC classification number: H01L23/49827 ,  H01L23/147 ,  H01L23/481 ,  H01L23/58 ,  H01L2224/16225

Abstract: Semiconductor devices and methods for forming a semiconductor device are disclosed. The semiconductor device includes a die. The die includes a die substrate having first and second major surfaces. The semiconductor device includes a power module disposed below the second major surface of the die substrate. The power module is electrically coupled to the die through through silicon via (TSV) contacts.

Abstract translation: 公开了用于形成半导体器件的半导体器件和方法。 该半导体器件包括一个管芯。 模具包括具有第一和第二主表面的模具基板。 半导体器件包括设置在管芯衬底的第二主表面下方的功率模块。 电源模块通过硅通孔（TSV）触点电连接到管芯。

公开(公告)号：US20130277810A1

公开(公告)日：2013-10-24

申请号：US13453762

申请日：2012-04-23

Applicant: Juan Boon Tan ,  Yeow Kheng Lim ,  Shao Ning Yuan ,  Soh Yun Siah

Inventor： Juan Boon Tan ,  Yeow Kheng Lim ,  Shao Ning Yuan ,  Soh Yun Siah

IPC: H01L29/02 ,  H01L21/768

CPC classification number: H01L23/3677 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices are formed with through silicon vias extending into the semiconductor substrate from a backside surface for improved heat dissipation. Embodiments include forming a cavity in a backside surface of a substrate, the substrate including a gate stack on a frontside surface, and filling the cavity with a thermally conductive material.

Abstract translation: 半导体器件通过从后侧表面延伸到半导体衬底中的硅通孔形成，以改善散热。 实施例包括在衬底的背面形成空腔，衬底包括在前表面上的栅叠层，并用导热材料填充空腔。

公开(公告)号：US08358007B2

公开(公告)日：2013-01-22

申请号：US12796610

申请日：2010-06-08

Applicant: Dong Kyun Sohn ,  Wuping Liu ,  Fan Zhang ,  Juan Boon Tan ,  Jing Hui Li ,  Bei Chao Zhang ,  Luying Du ,  Wei Liu ,  Yeow Kheng Lim

Inventor： Dong Kyun Sohn ,  Wuping Liu ,  Fan Zhang ,  Juan Boon Tan ,  Jing Hui Li ,  Bei Chao Zhang ,  Luying Du ,  Wei Liu ,  Yeow Kheng Lim

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/5329 ,  H01L21/3105 ,  H01L21/31155 ,  H01L21/76825 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76859 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A method of manufacture of an integrated circuit system includes: fabricating a substrate having an integrated circuit; applying a low-K dielectric layer over the integrated circuit; forming a via and a trench, in the low-K dielectric layer, over the integrated circuit; forming a structure surface by a chemical-mechanical planarization (CMP) process; and applying a direct implant to the structure surface for forming an implant layer and a metal passivation layer including repairing damage, to the low-K dielectric layer, caused by the CMP process.

Abstract translation: 集成电路系统的制造方法包括：制造具有集成电路的基板; 在集成电路上施加低K电介质层; 在低K电介质层中形成通孔和沟槽，在集成电路上; 通过化学机械平面化（CMP）工艺形成结构表面; 以及对由CMP工艺引起的用于形成植入层和金属钝化层的直接植入物施加到包括修复损伤的低K电介质层。

公开(公告)号：US20110266628A1

公开(公告)日：2011-11-03

申请号：US13182455

申请日：2011-07-14

Applicant: Vincent HO ,  Wenhe LIN ,  Young Way TEH ,  Yong Kong SIEW ,  Bei Chao ZHANG ,  Fan ZHANG ,  Haifeng SHENG ,  Juan Boon TAN

Inventor： Vincent HO ,  Wenhe LIN ,  Young Way TEH ,  Yong Kong SIEW ,  Bei Chao ZHANG ,  Fan ZHANG ,  Haifeng SHENG ,  Juan Boon TAN

IPC: H01L27/092 ,  H01L29/78

CPC classification number: H01L21/26506 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7845

Abstract: The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate.

Abstract translation: 本发明提供了一种通过在源/漏退火处理之前将栅极区域施加离子注入来在半导体器件衬底中引起应力的方法。 然后可以将栅极/漏极区域与栅极退火，由于所述离子注入将导致栅极在某些区域中膨胀。 结果，由栅极的所述膨胀引起的应力被转移到半导体衬底中的沟道区域。

公开(公告)号：US07993997B2

公开(公告)日：2011-08-09

申请号：US11865563

申请日：2007-10-01

Applicant: Vincent Ho ,  Wenhe Lin ,  Young Way Teh ,  Yong Kong Siew ,  Bei Chao Zhang ,  Fan Zhang ,  Haifeng Sheng ,  Juan Boon Tan

Inventor： Vincent Ho ,  Wenhe Lin ,  Young Way Teh ,  Yong Kong Siew ,  Bei Chao Zhang ,  Fan Zhang ,  Haifeng Sheng ,  Juan Boon Tan

IPC: H01L21/8238 ,  H01L21/336

CPC classification number: H01L21/26506 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7845

Abstract: The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate.

Abstract translation: 本发明提供了一种通过在源/漏退火处理之前将栅极区域施加离子注入来在半导体器件衬底中引起应力的方法。 然后可以将栅极/漏极区域与栅极退火，由于所述离子注入将导致栅极在某些区域中膨胀。 结果，由栅极的所述膨胀引起的应力被转移到半导体衬底中的沟道区域。

公开(公告)号：US20100001370A1

公开(公告)日：2010-01-07

申请号：US12168816

申请日：2008-07-07

Applicant: Haifeng Sheng ,  Fan Zhang ,  Juan Boon Tan ,  Bei Chao Zhang ,  Dong Kyun Sohn

Inventor： Haifeng Sheng ,  Fan Zhang ,  Juan Boon Tan ,  Bei Chao Zhang ,  Dong Kyun Sohn

IPC: H01L21/768 ,  H01L21/02 ,  H01L27/06

CPC classification number: H01L23/5223 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit system that includes: providing a substrate including front-end-of-line circuitry; forming a first conductive level including a first conductive trace over the substrate; forming a second conductive level spaced apart from the first conductive level and including a second conductive trace; and connecting the first conductive level to a third conductive level with a viabar that passes through the second conductive level without contacting the second conductive trace.

Abstract translation: 一种集成电路系统，包括：提供包括前端电路的基板; 形成包括在所述衬底上的第一导电迹线的第一导电电平; 形成与所述第一导电电平间隔开并包括第二导电迹线的第二导电电平; 以及将第一导电电平与通过第二导电电平而不接触第二导电迹线的viabar连接到第三导电电平。

公开(公告)号：US20090085122A1

公开(公告)日：2009-04-02

申请号：US11865563

申请日：2007-10-01

Applicant: Vincent Ho ,  Wenhe Lin ,  Young Way Teh ,  Yong Kong Siew ,  Bei Chao Zhang ,  Fan Zhang ,  Haifeng Sheng ,  Juan Boon Tan

Inventor： Vincent Ho ,  Wenhe Lin ,  Young Way Teh ,  Yong Kong Siew ,  Bei Chao Zhang ,  Fan Zhang ,  Haifeng Sheng ,  Juan Boon Tan

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/26506 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7845

Abstract: The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate.

Abstract translation: 本发明提供了一种通过在源/漏退火处理之前将栅极区域施加离子注入来在半导体器件衬底中引起应力的方法。 然后可以将栅极/漏极区域与栅极退火，由于所述离子注入将导致栅极在某些区域中膨胀。 结果，由栅极的所述膨胀引起的应力被转移到半导体衬底中的沟道区域。

公开(公告)号：US20080111238A1

公开(公告)日：2008-05-15

申请号：US11558342

申请日：2006-11-09

Applicant: Xianbin Wang ,  Juan Boon Tan ,  Liang-Choo Hsia ,  Teck Jung Tang ,  Huang Liu

Inventor： Xianbin Wang ,  Juan Boon Tan ,  Liang-Choo Hsia ,  Teck Jung Tang ,  Huang Liu

IPC: H01L23/52 ,  H01L21/4763

CPC classification number: H01L21/76835 ,  H01L21/76829 ,  H01L21/7684 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit processing system is provided including providing a substrate having an integrated circuit, forming an interconnect layer over the integrated circuit, applying a low-K dielectric layer over the interconnect layer, applying an ultra low-K dielectric layer over the low-K dielectric layer, forming an opening through the ultra low-K dielectric layer and the low-K dielectric layer to the interconnect layer, depositing an interconnect metal in the opening, and chemical-mechanical polishing the interconnect metal and the ultra low-K dielectric layer.

Abstract translation: 提供一种集成电路处理系统，包括提供具有集成电路的衬底，在集成电路上形成互连层，在互连层上施加低K电介质层，在低K电介质层上施加超低K电介质层 电介质层，通过超低K电介质层和低K电介质层形成开口到互连层，在开口中沉积互连金属，并对互连金属和超低K电介质层进行化学机械抛光 。

公开(公告)号：US07276440B2

公开(公告)日：2007-10-02

申请号：US10734423

申请日：2003-12-12

Applicant: Fan Zhang ,  Bei Chao Zhang ,  Wuping Liu ,  Kho Liep Chok ,  Liang Choo Hsia ,  Tae Jong Lee ,  Juan Boon Tan ,  Xian Bin Wang

Inventor： Fan Zhang ,  Bei Chao Zhang ,  Wuping Liu ,  Kho Liep Chok ,  Liang Choo Hsia ,  Tae Jong Lee ,  Juan Boon Tan ,  Xian Bin Wang

IPC: H01L23/04

CPC classification number: H01L23/562 ,  H01L23/3178 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

Abstract: In accordance with the objectives of the invention a new design and method for the implementation thereof is provided in the form of an “oxide ring”. A conventional die is provided with a guard ring or sealing ring, which surrounds and isolates the active surface area of an individual semiconductor die. The “oxide ring” of the invention surrounds the guard ring or sealing ring and forms in this manner a mechanical stress release buffer between the sawing paths of the die and the active surface area of the singulated individual semiconductor die.

Abstract translation: 根据本发明的目的，以“氧化物环”的形式提供了一种用于实施本发明的新设计和方法。 传统的模具设置有保护环或密封环，其围绕并隔离单个半导体管芯的有源表面积。 本发明的“氧化物环”围绕保护环或密封环，并以这种方式形成在管芯的锯切路径和单个化的半导体管芯的有源表面区域之间的机械应力释放缓冲器。