Invention Grant
US09449834B2 Method of fabricating semiconductor devices including PMOS devices having embedded SiGe
有权
制造包括具有嵌入SiGe的PMOS器件的半导体器件的方法
- Patent Title: Method of fabricating semiconductor devices including PMOS devices having embedded SiGe
- Patent Title (中): 制造包括具有嵌入SiGe的PMOS器件的半导体器件的方法
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Application No.: US13289983Application Date: 2011-11-04
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Publication No.: US09449834B2Publication Date: 2016-09-20
- Inventor: Qingsong Wei , Wei Lu , Wuping Liu , Yonggen He
- Applicant: Qingsong Wei , Wei Lu , Wuping Liu , Yonggen He
- Applicant Address: CN
- Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
- Current Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
- Current Assignee Address: CN
- Agency: Innovation Counsel LLP
- Priority: CN201110197909 20110715
- Main IPC: H01L21/3205
- IPC: H01L21/3205 ; H01L21/306 ; H01L21/265 ; H01L29/66 ; H01L29/78 ; H01L29/165 ; H01L21/308

Abstract:
A method of fabricating semiconductor device is provided. First, a recess having a substantially rectangular cross section is formed in a substrate. Then, oxide layers are formed on sidewalls and bottom of the recess by oxygen ion implantation process, wherein oxide layer on sidewalls of recess is thinner than oxide layer on bottom of recess. Thereafter, oxide layer on sidewalls of recess is completely removed, and only a portion of oxide layer on bottom of recess remains. Then, sidewalls of recess are shaped into Σ form by orientation selective wet etching using oxide layer remained on bottom of recess as a stop layer. Finally, oxide layer on bottom of recess is removed. By forming oxide layer on bottom of recess and using it as stop layer in subsequent orientation selective wet etching, the disclosed method can prevent a Σ-shaped recess with a cuspate bottom.
Public/Granted literature
- US20130017656A1 METHOD OF FABRICATING A SEMICONDUCTOR DEVICE Public/Granted day:2013-01-17
Information query
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