公开(公告)号：US06528351B1

公开(公告)日：2003-03-04

申请号：US09963337

申请日：2001-09-24

Applicant: Richard J. Nathan ,  William H. Shepherd

Inventor： Richard J. Nathan ,  William H. Shepherd

IPC: H01L2144

CPC classification number: H01L23/5389 ,  H01L24/24 ,  H01L24/45 ,  H01L24/48 ,  H01L24/82 ,  H01L24/96 ,  H01L25/0655 ,  H01L29/0657 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/24227 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48479 ,  H01L2224/82001 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10157 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/4554

Abstract: One or more integrated circuit chips each containing conductive pads on one surface, are embedded in a substrate such that the conductive pads are exposed and the one surface of each chip is substantially coplanar with a top surface of the substrate. Electrically conductive material is placed over the one surface, including conductive pads, of each chip and the top surface of the substrate and patterned, using standard semiconductor or printed circuit photolithographic and processing techniques to form an electrically conductive interconnect pattern connecting the one or more integrated circuit chips into an electronic system. When a single integrated circuit chip is to be embedded in a substrate, the invention makes possible the simultaneous manufacture of a plurality of such packaged integrated circuit chips in a single large substrate using standard semiconductor or printed circuit photolithographic and processing techniques and then singulating the large substrate into a plurality of smaller substrates, each containing a single integrated circuit chip. Likewise, when more than one integrated circuit chip is embedded in a substrate, a plurality of such structures can be manufactured in a single large substrate and then singulated into a plurality of smaller substrates, each containing more than one integrated circuit chips.

Abstract translation: 一个或多个在一个表面上包含导电焊盘的集成电路芯片被嵌入到衬底中，使得导电焊盘被暴露，并且每个芯片的一个表面与衬底的顶表面基本共面。 使用标准半导体或印刷电路光刻和处理技术，将导电材料放置在每个芯片的导电焊盘和基板的顶表面的一个表面上，并被图案化，以形成连接一个或多个集成 电路芯片进入电子系统。 当将单个集成电路芯片嵌入基板时，本发明使得可以使用标准半导体或印刷电路光刻和处理技术在单个大型基板中同时制造多个这样的封装集成电路芯片，然后将大的 衬底形成多个较小的衬底，每个衬底均包含单个集成电路芯片。 同样地，当多于一个的集成电路芯片嵌入到基板中时，可以在单个大的基板中制造多个这样的结构，然后将其分成多个较小的基板，每个较小的基板包含多于一个的集成电路芯片。

公开(公告)号：US5906043A

公开(公告)日：1999-05-25

申请号：US884823

申请日：1997-06-30

Applicant: James J. D. Lan ,  Steve S. Chiang ,  William H. Shepherd ,  Paul Y. F. Wu

Inventor： James J. D. Lan ,  Steve S. Chiang ,  William H. Shepherd ,  Paul Y. F. Wu

IPC: H05K1/00 ,  H05K3/00 ,  H05K3/02 ,  H05K3/18 ,  H05K3/40 ,  H05K3/46 ,  H01K3/10

CPC classification number: H05K3/4069 ,  H05K1/0293 ,  H05K3/0023 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/10689 ,  H05K2203/105 ,  H05K2203/1461 ,  H05K2203/1536 ,  H05K2203/173 ,  H05K3/025 ,  H05K3/181 ,  H05K3/4652 ,  Y10T29/49016 ,  Y10T29/49165

Abstract: In one embodiment, the steps for forming an electrical conductor between conductive layers of a printed circuit board include the following steps: (1) applying a first dielectric material on a first conductive layer; (2) forming a number of via holes at each of the predetermined locations in the first dielectric material at which an electrical conductor is to be formed; (3) selectively applying a second dielectric material to at least fill each of the via holes, to form a composite dielectric layer; (4) applying a second conductive layer on the composite dielectric layer; (5) etching the first conductive layer to form a first electrode; (6) etching the second conductive layer to form a second electrode; and (7) applying a programming voltage across the second dielectric material in each of the via holes to form an electrical conductor in each of the via holes, each electrical conductor connecting an electrode in the first conductive layer to an electrode in the second conductive layer.

Abstract translation: 在一个实施例中，用于在印刷电路板的导电层之间形成电导体的步骤包括以下步骤：（1）在第一导电层上施加第一介电材料; （2）在要形成电导体的第一介电材料中的每个预定位置处形成多个通孔; （3）选择性地施加第二电介质材料以至少填充每个通孔，以形成复合电介质层; （4）在复合介电层上施加第二导电层; （5）蚀刻第一导电层以形成第一电极; （6）蚀刻所述第二导电层以形成第二电极; 和（7）在每个通孔中的第二电介质材料上施加编程电压以在每个通孔中形成电导体，每个电导体将第一导电层中的电极连接到第二导电层中的电极 。

公开(公告)号：US5808351A

公开(公告)日：1998-09-15

申请号：US320145

申请日：1994-10-07

Applicant: Richard J. Nathan ,  James J. D. Lan ,  Steve S. Chiang ,  William H. Shepherd

Inventor： Richard J. Nathan ,  James J. D. Lan ,  Steve S. Chiang ,  William H. Shepherd

IPC: G01R1/04 ,  G01R1/06 ,  G01R31/28 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01R29/00 ,  H01R31/06 ,  H05K1/00 ,  H05K1/14 ,  H05K1/16 ,  H05K3/06 ,  H05K3/24 ,  H05K3/42 ,  H05K3/46 ,  H05K7/10 ,  H01L29/12

CPC classification number: G01R1/04 ,  H01L21/485 ,  H01L23/49827 ,  H01L23/5382 ,  H01R29/00 ,  H05K1/0293 ,  H05K7/1092 ,  G01R1/06 ,  G01R31/2863 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/13091 ,  H01R23/70 ,  H01R31/06 ,  H05K1/0289 ,  H05K1/029 ,  H05K1/0292 ,  H05K1/0298 ,  H05K1/141 ,  H05K1/167 ,  H05K2201/0305 ,  H05K2201/09763 ,  H05K2201/10181 ,  H05K2201/10212 ,  H05K2201/10689 ,  H05K2203/0542 ,  H05K2203/105 ,  H05K2203/1115 ,  H05K2203/173 ,  H05K2203/175 ,  H05K3/062 ,  H05K3/243 ,  H05K3/429 ,  H05K3/4611

Abstract: Two types of programmable elements, fuses and antifuses, are disclosed for forming an electrically programmable burn-in board in one embodiment and an electrically programmable device-under-test (DUT) card in another embodiment. Both types of programmable elements can also be used in a reconfiguration device for interconnecting electrical contacts in a first configuration to electrical contacts in a second configuration. The various embodiments of this invention include, for example, a component socket, a socket adapter, a cable, a cable adapter, a scrambler card for a burn-in board and a device-under-test card for a burn-in board. A method for forming a fuse is also disclosed.

Abstract translation: 公开了两种可编程元件，熔丝和反熔丝，用于在一个实施例中形成电可编程老化板，以及另一实施例中的电可编程器件测试（DUT）卡。 两种类型的可编程元件也可用于重构装置中，用于将第一配置中的电触点与第二配置中的电触点相互连接。 本发明的各种实施例包括例如组件插座，插座适配器，电缆，电缆适配器，用于老化板的加扰器卡和用于老化板的测试用设备卡。 还公开了一种用于形成熔丝的方法。

公开(公告)号：US5962815A

公开(公告)日：1999-10-05

申请号：US374941

申请日：1995-01-18

Applicant: James J. D. Lan ,  Steve S. Chiang ,  William H. Shepherd ,  Paul Y. F. Wu

Inventor： James J. D. Lan ,  Steve S. Chiang ,  William H. Shepherd ,  Paul Y. F. Wu

IPC: H05K1/00 ,  H05K3/00 ,  H05K3/02 ,  H05K3/18 ,  H05K3/40 ,  H05K3/46 ,  H01R9/09

CPC classification number: H05K3/4069 ,  H05K1/0293 ,  H05K3/0023 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/10689 ,  H05K2203/105 ,  H05K2203/1461 ,  H05K2203/1536 ,  H05K2203/173 ,  H05K3/025 ,  H05K3/181 ,  H05K3/4652 ,  Y10T29/49016 ,  Y10T29/49165

Abstract: A multilayered structure, such as a printed circuit board, includes a first conductive layer and a second conductive layer that are separated from each other by a dielectric layer. The dielectric layer is formed of a first material, such as a photoimagible polyimide and epoxy resin. The dielectric layer has a number of via holes that extend from the first conductive layer to the second conductive layer. The via holes are filled with a second material having a breakdown voltage less than a breakdown voltage of the first material included in the dielectric layer to form an antifuse. The second material in the via holes can be, for example, a conductive epoxy resin or a polymer loaded with conductive particles (also referred to as "conductive paste").

Abstract translation: 诸如印刷电路板的多层结构包括通过电介质层彼此分离的第一导电层和第二导电层。 电介质层由第一材料形成，例如光可塑性聚酰亚胺和环氧树脂。 电介质层具有从第一导电层延伸到第二导电层的多个通孔。 通孔填充有具有小于包含在电介质层中的第一材料的击穿电压的击穿电压以形成反熔丝的第二材料。 通孔中的第二材料可以是例如导电环氧树脂或负载有导电颗粒的聚合物（也称为“导电糊”）。

公开(公告)号：US5834824A

公开(公告)日：1998-11-10

申请号：US405259

申请日：1995-03-14

Applicant: William H. Shepherd ,  Steve S. Chiang ,  John Y. Xie

Inventor： William H. Shepherd ,  Steve S. Chiang ,  John Y. Xie

IPC: G01R1/04 ,  G01R1/06 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01R29/00 ,  H05K1/00 ,  H05K1/14 ,  H05K1/16 ,  H05K3/06 ,  H05K3/24 ,  H05K3/42 ,  H05K3/46 ,  H05K7/10 ,  H01L27/02

CPC classification number: H05K7/1092 ,  G01R1/04 ,  H01L21/485 ,  H01L23/49827 ,  H01L23/5252 ,  H01L23/5382 ,  H01R29/00 ,  H05K1/0293 ,  G01R1/06 ,  H01L2924/0002 ,  H01R23/70 ,  H05K1/0289 ,  H05K1/029 ,  H05K1/0298 ,  H05K1/141 ,  H05K1/167 ,  H05K2201/0305 ,  H05K2201/09763 ,  H05K2201/10181 ,  H05K2201/10212 ,  H05K2201/10689 ,  H05K2203/0542 ,  H05K2203/105 ,  H05K2203/1115 ,  H05K2203/173 ,  H05K2203/175 ,  H05K3/062 ,  H05K3/243 ,  H05K3/429 ,  H05K3/4611

Abstract: A novel antifuse includes a composite of conductive particles dispersed throughout a nonconductive matrix, which composite is located inside an antifuse via. The antifuse via is defined by a dielectric layer that separates two electrodes. The electrodes can be located in the same conductive layer plane (typically parallel to and isolated from one another) or in two different conductive planes (typically formed transverse to one another and separated by a dielectric with an antifuse via formed therein). The electrodes can be coupled to, for example, active or passive regions of the integrated circuit. One embodiment of an antifuse (also called "composite antifuse") has only the composite in an antifuse via between the two conductive layers. Another embodiment of an antifuse (also called "hybrid antifuse") includes in addition to the composite, one or more thin dielectric layers also located in the antifuse via between the two conductive layers.

Abstract translation: 一种新颖的反熔丝包括分散在整个非导电基质中的导电颗粒的复合物，该复合材料位于反熔丝通孔内部。 反熔丝通孔由分离两个电极的电介质层限定。 电极可以位于相同的导电层平面（通常彼此平行并彼此隔离）或两个不同的导电平面（通常形成为彼此横向并由其中形成有反熔丝通孔的电介质隔开）。 电极可以耦合到例如集成电路的有源或无源区域。 反熔丝（也称为“复合反熔丝”）的一个实施例仅在两个导电层之间的反熔丝通孔中具有复合材料。 反熔丝（也称为“混合反熔丝”）的另一实施例除了复合材料之外还包括一个或多个薄介电层，其也位于两个导电层之间的反熔丝中。

公开(公告)号：US5536672A

公开(公告)日：1996-07-16

申请号：US950795

申请日：1992-09-24

Applicant: William D. Miller ,  Joseph T. Evans ,  Wayne I. Kinney ,  William H. Shepherd

Inventor： William D. Miller ,  Joseph T. Evans ,  Wayne I. Kinney ,  William H. Shepherd

IPC: H01L27/115 ,  H01L21/70

CPC classification number: H01L27/11502

Abstract: A ferroelectric capacitor structure is designed for fabrication together with MOS devices on a semiconductor substrate. The ferroelectric capacitor includes a diffusion barrier above the surface of the substrate for preventing the materials of the ferroelectric capacitor from contaminating the substrate or MOS devices. The ferroelectric capacitor comprises a bottom electrode, a thin film ferroelectric layer and a top electrode. An interlayer dielectric is formed to cover portions of the ferroelectric thin film and provide an opening therethrough for the top electrode. A ferroelectric memory cell comprises a field effect transistor together with a ferroelectric capacitor fabricated on a semiconductor substrate. In one configuration, the ferroelectric capacitor is offset from the field effect transistor, while in another configuration, the ferroelectric capacitor is substantially above the field effect transistor to provide greater density.

Abstract translation: 铁电电容器结构被设计用于与半导体衬底上的MOS器件一起制造。 铁电电容器包括在衬底表面上方的扩散阻挡层，用于防止铁电电容器的材料污染衬底或MOS器件。 铁电电容器包括底电极，薄膜铁电层和顶电极。 形成层间电介质以覆盖铁电薄膜的部分，并提供用于顶部电极的开口。 铁电存储单元包括场效应晶体管和制造在半导体衬底上的铁电电容器。 在一种配置中，铁电电容器偏离场效应晶体管，而在另一种配置中，铁电电容器基本上高于场效应晶体管，以提供更大的密度。

公开(公告)号：US4982309A

公开(公告)日：1991-01-01

申请号：US380942

申请日：1989-07-17

Applicant: William H. Shepherd

Inventor： William H. Shepherd

IPC: B01J23/46 ,  H01B3/12 ,  H01G4/008 ,  H01G4/12 ,  H01G4/33 ,  H01G7/06 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/01 ,  H01L27/04 ,  H01L27/105 ,  H01L27/108 ,  H01L39/00 ,  H01L39/24 ,  H01L41/22

CPC classification number: H01G4/008 ,  H01L27/016 ,  H01L39/2474 ,  H01L41/29 ,  Y10T29/435 ,  Y10T428/268

Abstract: Electrodes composed of ruthenium, iridium, osmium, or rhodium and the electrically conductive oxides of these metals are particularly well-suited to use in electrical ceramic oxide devices because of the low resistivity of the oxides and the stability of the oxides under the processing conditions necessary to optimize performance of electrical ceramic oxide materials.

公开(公告)号：US4151540A

公开(公告)日：1979-04-24

申请号：US858572

申请日：1977-12-08

Applicant: Wendell B. Sander ,  William H. Shepherd

Inventor： Wendell B. Sander ,  William H. Shepherd

IPC: H01L21/265 ,  H01L29/06 ,  H01L29/10 ,  H01L29/72

CPC classification number: H01L29/0615 ,  H01L21/26513 ,  H01L29/1004

Abstract: High beta, high frequency transistors require very narrow and high resistance base structures, thereby placing a low limit of collector-emitter voltages that may be used without encountering "punch-through" breakdown. This invention permits the use of normal collector-emitter voltages without danger of punch-through problems by injecting into the high resistance base material an impurity grid that serves both as an electrostatic shield to increase the voltage breakdown level, and as a means of reducing the apparent lateral base resistance, thereby further increasing the high frequency capability of the device without degrading the high beta characteristics.

Abstract translation: 高β晶体管需要非常窄且高电阻的基极结构，从而可以在不会发生“穿通”故障的情况下使用集电极 - 发射极电压的下限。 本发明允许使用正常的集电极 - 发射极电压，而不会出现穿通问题的危险，通过将高电阻基底材料注入用作静电屏蔽以增加电压击穿电平的杂质栅格，并且作为减少 表观侧基电阻，从而进一步增加器件的高频能力而不降低高β特性。

公开(公告)号：US06034427A

公开(公告)日：2000-03-07

申请号：US14693

申请日：1998-01-28

Applicant: James J. D. Lan ,  Steve S. Chiang ,  Paul Y. F. Wu ,  William H. Shepherd ,  John Y. Xie ,  Hang Jiang

Inventor： James J. D. Lan ,  Steve S. Chiang ,  Paul Y. F. Wu ,  William H. Shepherd ,  John Y. Xie ,  Hang Jiang

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/12

CPC classification number: H01L24/06 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49883 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05647 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/48647 ,  H01L2224/49109 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/0106 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025

Abstract: An integrated circuit (IC) package substrate has a dielectric layer and a micro filled via formed substantially in the center of a hole in the dielectric layer. The IC package substrate has at least one chip bonding pad and one ball attach pad that are electrically coupled to each other by the micro filled via. The micro filled via is formed of a material called a "micro filled via material" that includes a binding material and optionally includes a number of particles (between 0%-90% by volume) dispersed in the binding material. The binding material can be any material, such as a polymer that is either conductive or nonconductive. The particles can be formed of any conductive material, such as a conductive polymer or a conductive metal (e.g. copper or gold). An electrical conductor can be originally formed simply by contact between conductive particles located adjacent to each other. In an optional step, the micro filled via is subjected to a programming current (in a step called "programming") to lower the resistance of an originally formed electrical conductor, or to originally form an electrical conductor by break down of a dielectric material. The IC package substrate can be formed in either a cavity up or a cavity down configuration.

Abstract translation: 集成电路（IC）封装衬底具有基本上形成在电介质层中的孔的中心的电介质层和微填充通孔。 IC封装基板具有至少一个芯片焊盘和一个通过微型填充通孔彼此电耦合的焊球附着焊盘。 微填充通孔由称为“微填充通孔材料”的材料形成，其包括粘合材料，并且任选地包括分散在粘合材料中的许多颗粒（介于0％-90％之间）。 粘合材料可以是任何材料，例如导电或不导电的聚合物。 颗粒可由任何导电材料形成，例如导电聚合物或导电金属（例如铜或金）。 电导体本来可以简单地通过彼此相邻的导电颗粒之间的接触形成。 在可选步骤中，微填充通孔经受编程电流（在称为“编程”的步骤中）以降低原始形成的电导体的电阻，或者通过介电材料的分解原本形成电导体。 IC封装基板可以形成为空腔向上或空腔向下配置。

公开(公告)号：US5767575A

公开(公告)日：1998-06-16

申请号：US543982

申请日：1995-10-17

Applicant: James J. D. Lan ,  Steve S. Chiang ,  Paul Y. F. Wu ,  William H. Shepherd ,  John Y. Xie ,  Hang Jiang

Inventor： James J. D. Lan ,  Steve S. Chiang ,  Paul Y. F. Wu ,  William H. Shepherd ,  John Y. Xie ,  Hang Jiang

IPC: H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L23/50 ,  H01L23/12

CPC classification number: H01L24/73 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/05 ,  H01L24/06 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48599 ,  H01L2224/49109 ,  H01L2224/49173 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025

Abstract: An integrated circuit (IC) package substrate has a dielectric layer and a micro filled via formed substantially in the center of a hole in the dielectric layer. The IC package substrate has at least one chip bonding pad and one ball attach pad that are electrically coupled to each other by the micro filled via. The micro filled via is formed of a material called a "micro filled via material" that includes a binding material and optionally includes a number of particles (between 0%-90% by volume) dispersed in the binding material. The binding material can be any material, such as a polymer that is either conductive or nonconductive. The particles can be formed of any conductive material, such as a conductive polymer or a conductive metal (e.g. copper or gold). An electrical conductor can be originally formed simply by contact between conductive particles located adjacent to each other. In an optional step, the micro filled via is subjected to a programming current (in a step called "programming") to lower the resistance of an originally formed electrical conductor, or to originally form an electrical conductor by break down of a dielectric material. The IC package substrate can be formed in either a cavity up or a cavity down configuration.