公开(公告)号：US08557692B2

公开(公告)日：2013-10-15

申请号：US12686246

申请日：2010-01-12

Applicant: Chun Hsiung Tsai ,  Chien-Chang Su ,  Tsung-Hung Li ,  Da-Wen Lin ,  Wen-Sheh Huang

Inventor： Chun Hsiung Tsai ,  Chien-Chang Su ,  Tsung-Hung Li ,  Da-Wen Lin ,  Wen-Sheh Huang

IPC: H01L21/40 ,  H01L21/02

CPC classification number: H01L29/7848 ,  H01L21/26513 ,  H01L21/823821 ,  H01L29/66795 ,  H01L29/66803

Abstract: A method of forming an integrated circuit includes providing a semiconductor wafer; and forming a fin field-effect transistor (FinFET) including implanting the semiconductor wafer using a hot-implantation to form an implanted region in the FinFET. The implanted region comprises a region selected from the group consisting essentially of a lightly doped source and drain region, a pocket region, and a deep source drain region.

Abstract translation: 一种形成集成电路的方法包括：提供半导体晶片; 以及形成鳍状场效应晶体管（FinFET），其包括使用热注入植入所述半导体晶片以在所述FinFET中形成注入区域。 注入区域包括从基本上由轻掺杂的源极和漏极区域，口袋区域和深源极漏极区域组成的组中选择的区域。

公开(公告)号：US20130119480A1

公开(公告)日：2013-05-16

申请号：US13294251

申请日：2011-11-11

Applicant: King-Yuen Wong ,  Chia-Pin Lin ,  Chia-Yu Lu ,  Yi-Cheng Tsai ,  Da-Wen Lin ,  Kuo-Feng Yu

Inventor： King-Yuen Wong ,  Chia-Pin Lin ,  Chia-Yu Lu ,  Yi-Cheng Tsai ,  Da-Wen Lin ,  Kuo-Feng Yu

IPC: H01L29/772 ,  H01L21/02 ,  H01L29/02

CPC classification number: H01L28/20 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823437 ,  H01L27/0629 ,  H01L29/66545 ,  H01L29/8605

Abstract: A semiconductor device includes a substrate including an isolation region, and a resistor disposed over the isolation region, wherein the resistor includes an implant with an inverse box-like dopant profile that minimizes resistance variation from subsequent planarization variation. A contact is disposed over the resistor. A method of fabricating such a semiconductor device is also provided.

Abstract translation: 半导体器件包括包括隔离区域的衬底和设置在隔离区域上的电阻器，其中电阻器包括具有反向盒状掺杂物分布的植入物，其使得电阻变化与随后的平坦化变化最小化。 触点设置在电阻上。 还提供了一种制造这种半导体器件的方法。

公开(公告)号：US08426923B2

公开(公告)日：2013-04-23

申请号：US12797382

申请日：2010-06-09

Applicant: Tung Ying Lee ,  Li-Wen Weng ,  Chien-Tai Chan ,  Da-Wen Lin ,  Hsien-Chin Lin

Inventor： Tung Ying Lee ,  Li-Wen Weng ,  Chien-Tai Chan ,  Da-Wen Lin ,  Hsien-Chin Lin

IPC: H01L29/423

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/785

Abstract: A system and method for manufacturing multiple-gate semiconductor devices is disclosed. An embodiment comprises multiple fins, wherein intra-fin isolation regions extend into the substrate less than inter-fin isolation regions. Regions of the multiple fins not covered by the gate stack are removed and source/drain regions are formed from the substrate so as to avoid the formation of voids between the fins in the source/drain region.

Abstract translation: 公开了一种用于制造多栅极半导体器件的系统和方法。 一个实施例包括多个散热片，其中散热片内隔离区域延伸到小于鳍间隔离区域的衬底内。 去除未被栅极堆叠覆盖的多个鳍片的区域，并且从衬底形成源极/漏极区域，以避免在源极/漏极区域中的鳍片之间形成空隙。

公开(公告)号：US08383513B2

公开(公告)日：2013-02-26

申请号：US12898037

申请日：2010-10-05

Applicant: Chun Hsiung Tsai ,  Chii-Ming Wu ,  Da-Wen Lin

Inventor： Chun Hsiung Tsai ,  Chii-Ming Wu ,  Da-Wen Lin

IPC: H01L21/44 ,  H01L21/8238

CPC classification number: H01L21/324 ,  H01L21/26513 ,  H01L21/67248

Abstract: Rapid thermal annealing methods and systems for annealing patterned substrates with minimal pattern effect on substrate temperature non-uniformity are provided. The rapid thermal annealing system includes a front-side heating source and a backside heating source. The backside heating source of the rapid thermal annealing system supplies a dominant amount of heat to bring the substrate temperature to the peak annealing temperature. The front-side heating source contributes to heat up the environment near the front-side of the substrate to a temperature lower than about 100° C. to about 200° C. less than the peak annealing temperature. The asymmetric front-side and backside heating for rapid thermal annealing reduce or eliminate pattern effect and improve WIW and WID device performance uniformity.

Abstract translation: 提供了用于退火图案化衬底的快速热退火方法和系统，对衬底温度的不均匀性具有最小的图案效应。 快速热退火系统包括前侧加热源和背面加热源。 快速热退火系统的背面加热源提供显着的热量以使衬底温度达到峰值退火温度。 前侧加热源有助于将基板前侧附近的环境加热至比峰退火温度低约100℃至约200℃的温度。 用于快速热退火的不对称前侧和后侧加热减少或消除图案效应，并提高WIW和WID器件的性能均匀性。

公开(公告)号：US08357579B2

公开(公告)日：2013-01-22

申请号：US13042539

申请日：2011-03-08

Applicant: King-Yuen Wong ,  Ming-Lung Cheng ,  Chien-Tai Chan ,  Da-Wen Lin ,  Chung-Cheng Wu

Inventor： King-Yuen Wong ,  Ming-Lung Cheng ,  Chien-Tai Chan ,  Da-Wen Lin ,  Chung-Cheng Wu

IPC: H01L21/335 ,  H01L21/336 ,  H01L29/76 ,  H01L21/02

CPC classification number: H01L29/7833 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7834

Abstract: A method of forming an integrated circuit includes forming a gate structure over a substrate. Portions of the substrate are removed to form recesses adjacent to the gate structure. A dopant-rich layer having first type dopants is formed on a sidewall and a bottom of each of the recesses. A silicon-containing material structure is formed in each of the recesses. The silicon-containing material structure has second type dopants. The second type dopants are opposite to the first type dopants.

Abstract translation: 形成集成电路的方法包括在衬底上形成栅极结构。 去除基板的一部分以形成与栅极结构相邻的凹部。 在每个凹部的侧壁和底部形成有具有第一类型掺杂剂的富掺杂层。 在每个凹部中形成含硅材料结构。 含硅材料结构具有第二种掺杂剂。 第二种掺杂剂与第一种掺杂剂相反。

公开(公告)号：US20130017678A1

公开(公告)日：2013-01-17

申请号：US13183909

申请日：2011-07-15

Applicant: Chun Hsiung TSAI ,  Xiong-Fei YU ,  Yu-Lien HUANG ,  Da-Wen LIN

Inventor： Chun Hsiung TSAI ,  Xiong-Fei YU ,  Yu-Lien HUANG ,  Da-Wen LIN

IPC: H01L21/263

CPC classification number: H01L21/324 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7833

Abstract: Multi-stage preheat high-temperature anneal processes after the deposition of the gate dielectric layer(s) reduce the number of interfacial sites and improve the negative bias temperature instability (NTBI) performance of a p-type metal-oxide-semiconductor transistor (PMOS). The gate dielectric layers may include an interfacial oxide layer and a high-k dielectric layer. The multi-stage preheat is designed to reduce dopant deactivation and to improve inter-mixing between the interfacial oxide layer and the high-k dielectric layer. The high-temperature anneal is used to reduce the number of interfacial sites at the interface between the silicon substrate and the interfacial oxide layer.

Abstract translation: 在沉积栅极电介质层之后的多级预热高温退火工艺减少界面位置的数量并改善p型金属氧化物半导体晶体管（PMOS）的负偏压温度不稳定性（NTBI）性能 ）。 栅极电介质层可以包括界面氧化物层和高k电介质层。 多级预热设计用于减少掺杂剂失活并改善界面氧化物层和高k电介质层之间的相互混合。 高温退火用于减少硅衬底和界面氧化物层之间界面处的界面位置数。

公开(公告)号：US08283734B2

公开(公告)日：2012-10-09

申请号：US12757465

申请日：2010-04-09

Applicant: Chung-Yu Chiang ,  Da-Wen Lin ,  Shyh-Wei Wang

Inventor： Chung-Yu Chiang ,  Da-Wen Lin ,  Shyh-Wei Wang

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/0847 ,  H01L21/266 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/6659 ,  H01L29/7833

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device are disclosed. An exemplary method includes providing a substrate; forming a first gate over the substrate for a first device having a first threshold voltage characteristic, the first gate including a first material having a first-type work function; forming a second gate over the substrate for a second device having a second threshold voltage characteristic that is greater than the first threshold voltage characteristic, the second gate including a second material having a second-type work function that is opposite the first-type work function; and configuring the first device and the second device as a same channel type device.

Abstract translation: 公开了一种用于制造集成电路器件的集成电路器件和方法。 一种示例性方法包括提供基底; 在具有第一阈值电压特性的第一器件的衬底上形成第一栅极，所述第一栅极包括具有第一类型功函数的第一材料; 在所述衬底上形成具有大于所述第一阈值电压特性的第二阈值电压特性的第二器件的第二栅极，所述第二栅极包括具有与所述第一类型功函数相反的第二类型功函数的第二材料 ; 以及将所述第一设备和所述第二设备配置为相同的信道类型设备。

公开(公告)号：US20120086053A1

公开(公告)日：2012-04-12

申请号：US12900626

申请日：2010-10-08

Applicant: Chih-Hung TSENG ,  Da-Wen LIN ,  Chien-Tai CHAN ,  Chia-Pin LIN ,  Li-Wen WENG ,  An-Shen CHANG ,  Chung-Cheng WU

Inventor： Chih-Hung TSENG ,  Da-Wen LIN ,  Chien-Tai CHAN ,  Chia-Pin LIN ,  Li-Wen WENG ,  An-Shen CHANG ,  Chung-Cheng WU

IPC: H01L29/78 ,  H01L21/76

CPC classification number: H01L29/7851 ,  H01L29/66795 ,  H01L29/7853

Abstract: A transistor includes a notched fin covered under a shallow trench isolation layer. One or more notch may be used, the size of which may vary along a lateral direction of the fin. In some embodiments, The notch is formed using anisotropic wet etching that is selective according to silicon orientation. Example wet etchants are tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH).

Abstract translation: 晶体管包括覆盖在浅沟槽隔离层下面的切口鳍。 可以使用一个或多个凹口，其尺寸可以沿翅片的横向方向变化。 在一些实施例中，使用根据硅取向选择性的各向异性湿蚀刻形成凹口。 实例湿蚀刻剂是氢氧化四甲基铵（TMAH）或氢氧化钾（KOH）。

公开(公告)号：US08143680B2

公开(公告)日：2012-03-27

申请号：US12778912

申请日：2010-05-12

Applicant: Da-Wen Lin ,  Ying-Shiou Lin ,  Shyh-Wei Wang ,  Li-Ping Huang ,  Ying-Keung Leung ,  Carlos H. Diaz

Inventor： Da-Wen Lin ,  Ying-Shiou Lin ,  Shyh-Wei Wang ,  Li-Ping Huang ,  Ying-Keung Leung ,  Carlos H. Diaz

IPC: H01L29/66 ,  H01L29/76 ,  H01L21/336

CPC classification number: H01L29/7391 ,  H01L29/0657 ,  H01L29/42312 ,  H01L29/66356

Abstract: A gated-diode semiconductor device or similar component and a method of fabricating the device. The device features a gate structure disposed on a substrate over a channel and adjacent a source and a drain. The top of the source or drain region, or both, are formed so as to be at a higher elevation, in whole or in part, than the bottom of the gate structure. This configuration may be achieved by overlaying the gate structure and substrate with a profile layer that guides a subsequent etch process to create a sloped profile. The source and drain, if both are present, may be symmetrical or asymmetrical. This configuration significantly reduces dopant encroachment and, as a consequence, reduces junction leakage.

Abstract translation: 门控二极管半导体器件或类似部件及其制造方法。 该器件具有栅极结构，该栅极结构设置在通道上的衬底上并且与源极和漏极相邻。 源极或漏极区域或两者的顶部形成为比栅极结构的底部全部或部分更高的高度。 这种配置可以通过用引导随后的蚀刻工艺来形成倾斜轮廓的轮廓层覆盖栅极结构和衬底来实现。 如果两者都存在，则源极和漏极可以是对称的或非对称的。 这种配置显着地减少了掺杂剂的侵蚀，结果减少了结漏电。

公开(公告)号：US20110278676A1

公开(公告)日：2011-11-17

申请号：US12780124

申请日：2010-05-14

Applicant: Ming-Lung Cheng ,  Yen-Chun Lin ,  Da-Wen Lin

Inventor： Ming-Lung Cheng ,  Yen-Chun Lin ,  Da-Wen Lin

IPC: H01L21/28 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/511 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7847 ,  H01L29/7848

Abstract: An apparatus includes a substrate having a strained channel region, a dielectric layer over the channel region, first and second conductive layers over the dielectric layer having a characteristic with a first value, and a strain-inducing conductive layer between the conductive layers having the characteristic with a second value different from the first value. A different aspect involves an apparatus that includes a substrate, first and second projections extending from the substrate, the first projection having a tensile-strained first channel region and the second projection having a compression-strained second channel region, and first and second gate structures engaging the first and second projections, respectively. The first gate structure includes a dielectric layer, first and second conductive layers over the dielectric layer, and a strain-inducing conductive layer between the conductive layers. The second gate structure includes a high-k dielectric layer adjacent the second channel region, and a metal layer.

Abstract translation: 一种装置包括具有应变通道区的衬底，沟道区上的电介质层，介电层上的第一和第二导电层具有第一值的特性，以及具有特征的导电层之间的应变诱发导电层 具有与第一值不同的第二值。 不同的方面涉及一种装置，其包括衬底，从衬底延伸的第一和第二突起，第一突起具有拉伸应变的第一沟道区，第二突起具有压缩应变的第二沟道区，以及第一和第二栅结构 分别接合第一和第二突起。 第一栅极结构包括电介质层，电介质层上的第一和第二导电层，以及在导电层之间的应变感应导电层。 第二栅极结构包括与第二沟道区相邻的高k电介质层和金属层。