公开(公告)号：US08877602B2

公开(公告)日：2014-11-04

申请号：US13156939

申请日：2011-06-09

Applicant: Yu-Lien Huang ,  Chun Hsiung Tsai ,  Chii-Ming Wu ,  Ziwei Fang

Inventor： Yu-Lien Huang ,  Chun Hsiung Tsai ,  Chii-Ming Wu ,  Ziwei Fang

IPC: H01L21/76 ,  H01L21/762

CPC classification number: H01L21/76229

Abstract: The embodiments described provide mechanisms for doping oxide in the STIs with carbon to make etch rate in the narrow and wide structures equal and also to make corners of wide STIs strong. Such carbon doping can be performed by ion beam (ion implant) or by plasma doping. The hard mask layer can be used to protect the silicon underneath from doping. By using the doping mechanism, the even surface topography of silicon and STI enables patterning of gate structures and ILD0 gapfill for advanced processing technology.

Abstract translation: 所描述的实施例提供了用碳掺杂STI中的氧化物的机制，以使窄和宽结构中的蚀刻速率相等并且也使得宽STI的拐角变强。 这种碳掺杂可以通过离子束（离子注入）或通过等离子体掺杂来进行。 硬掩模层可用于保护下面的硅不被掺杂。 通过使用掺杂机制，硅和STI的均匀表面形貌使得门结构和ILD0间隙填充的图案化能够用于先进的加工技术。

公开(公告)号：US20140191333A1

公开(公告)日：2014-07-10

申请号：US13735949

申请日：2013-01-07

Applicant: Chun-Wei CHANG ,  Yi-An LIN ,  Neng-Kuo CHEN ,  Sey-Ping SUN ,  Clement Hsingjen WANN ,  Yu-Lien HUANG

Inventor： Chun-Wei CHANG ,  Yi-An LIN ,  Neng-Kuo CHEN ,  Sey-Ping SUN ,  Clement Hsingjen WANN ,  Yu-Lien HUANG

IPC: H01L29/06 ,  H01L21/02

CPC classification number: H01L21/022 ,  H01L29/66545

Abstract: This description relates to a method including forming an interlayer dielectric (ILD) layer and a dummy gate structure over a substrate and forming a cavity in a top portion of the ILD layer. The method further includes forming a protective layer to fill the cavity. The method further includes planarizing the protective layer. A top surface of the planarized protective layer is level with a top surface of the dummy gate structure. This description also relates to a semiconductor device including first and second gate structures and an ILD layer formed on a substrate. The semiconductor device further includes a protective layer formed on the ILD layer, the protective layer having a different etch selectivity than the ILD layer, where a top surface of the protective layer is level with the top surfaces of the first and second gate structures.

Abstract translation: 该描述涉及包括在衬底上形成层间电介质（ILD）层和虚拟栅极结构并在ILD层的顶部形成腔的方法。 该方法还包括形成保护层以填充空腔。 该方法还包括平坦化保护层。 平坦化保护层的顶表面与虚拟栅结构的顶表面平齐。 该描述还涉及包括第一和第二栅极结构以及形成在衬底上的ILD层的半导体器件。 半导体器件还包括形成在ILD层上的保护层，保护层具有与ILD层不同的蚀刻选择性，其中保护层的顶表面与第一和第二栅极结构的顶表面平齐。

公开(公告)号：US20120315733A1

公开(公告)日：2012-12-13

申请号：US13157179

申请日：2011-06-09

Applicant: Yu-Lien HUANG ,  Ziwei FANG ,  Tsan-Chun WANG ,  Chii-Ming WU ,  Chun Hsiung TSAI

Inventor： Yu-Lien HUANG ,  Ziwei FANG ,  Tsan-Chun WANG ,  Chii-Ming WU ,  Chun Hsiung TSAI

IPC: H01L21/8238 ,  H01L21/321 ,  H01L21/30 ,  B82Y40/00

CPC classification number: H01L21/823814 ,  H01L21/0337 ,  H01L21/31155 ,  H01L21/32139 ,  H01L21/823807

Abstract: A hard mask layer with a limited thickness is formed over a gate electrode layer. A treatment is provided on the hard mask layer to transform the hard mask layer to be more resistant to wet etching solution. A patterning is provided on the treated hard mask layer and the gate electrode to from a gate structure.

Abstract translation: 在栅电极层上形成具有有限厚度的硬掩模层。 在硬掩模层上提供处理，以将硬掩模层转变为更耐湿蚀刻溶液。 在经处理​​的硬掩模层和栅电极上提供从栅极结构构图。

公开(公告)号：US20110006390A1

公开(公告)日：2011-01-13

申请号：US12757203

申请日：2010-04-09

Applicant: Yu-Lien HUANG ,  Han-Pin CHUNG ,  Shiang-Bau WANG

Inventor： Yu-Lien HUANG ,  Han-Pin CHUNG ,  Shiang-Bau WANG

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L21/76224

Abstract: A method for forming an STI structure is provided. In one embodiment, a trench is formed in a substrate, the trench having a first sidewall and a second sidewall opposite the first sidewall, the sidewalls extending down to a bottom portion of the trench. An insulating material is deposited to line the surfaces of the sidewalls and the bottom portion. The insulating material proximate the top portions and the bottom portion of the trench are thereafter etched back. The insulating material is deposited to line the inside surfaces of the trench at a rate sufficient to allow a first protruding insulating material deposited on the first sidewall and a second protruding insulating material deposited on the second sidewall to approach theretogether. The steps of etching back and depositing are repeated to have the first and second protruding materials abut, thereby forming a void near the bottom of the trench.

Abstract translation: 提供了一种用于形成STI结构的方法。 在一个实施例中，在衬底中形成沟槽，沟槽具有第一侧壁和与第一侧壁相对的第二侧壁，所述侧壁向下延伸到沟槽的底部。 沉积绝缘材料以对侧壁和底部的表面进行排列。 此后，接近顶部和沟槽底部的绝缘材料被回蚀。 绝缘材料被沉积成以足以允许沉积在第一侧壁上的第一突出绝缘材料和沉积在第二侧壁上的第二突出绝缘材料一齐接近的速率对沟槽的内表面进行排列。 重复蚀刻回落和沉积的步骤以使第一和第二突出材料抵接，从而在沟槽的底部附近形成空隙。

公开(公告)号：US20070190730A1

公开(公告)日：2007-08-16

申请号：US11352588

申请日：2006-02-13

Applicant: Yu-Lien Huang ,  Jim Huang ,  Ling-Yen Yeh ,  Hun-Jan Tao

Inventor： Yu-Lien Huang ,  Jim Huang ,  Ling-Yen Yeh ,  Hun-Jan Tao

IPC: H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636

Abstract: A method for improving uniformity of stressors of MOS devices is provided. The method includes forming a gate dielectric over a semiconductor substrate, forming a gate electrode on the gate dielectric, forming a spacer on respective sidewalls of the gate electrode and the gate dielectric, forming a recess in the semiconductor adjacent the spacer, and depositing SiGe in the recess to form a SiGe stressor. The method further includes etching the SiGe stressor to improve the uniformity of SiGe stressors.

Abstract translation: 提供了一种改善MOS器件的应力源均匀性的方法。 该方法包括在半导体衬底上形成栅极电介质，在栅极电介质上形成栅电极，在栅电极和栅极电介质的相应侧壁上形成间隔物，在邻近间隔物的半导体中形成凹陷，并将SiGe沉积在 凹陷形成SiGe应激源。 该方法还包括蚀刻SiGe应力器以改善SiGe应力的均匀性。

公开(公告)号：US20070013070A1

公开(公告)日：2007-01-18

申请号：US11159709

申请日：2005-06-23

Applicant: Mong Liang ,  Hun-Jan Tao ,  Jim Huang ,  Ling-Yen Yeh ,  Yu-Lien Huang

Inventor： Mong Liang ,  Hun-Jan Tao ,  Jim Huang ,  Ling-Yen Yeh ,  Yu-Lien Huang

IPC: H01L23/52

CPC classification number: H01L21/02123 ,  H01L21/3185 ,  H01L27/10894 ,  H01L27/11

Abstract: Novel etch stop layers for semiconductor devices and methods of forming thereof are disclosed. In one embodiment, an etch stop layer comprises tensile or compressive stress. In another embodiments, etch stop layers are formed having a first thickness in a first region of a workpiece and at least one second thickness in a second region of a workpiece, wherein the at least one second thickness is different than the first thickness. The etch stop layer may be thicker over top surfaces than over sidewall surfaces. The etch stop layer may be thicker over widely-spaced feature regions and thinner over closely-spaced feature regions.

Abstract translation: 公开了用于半导体器件的新型蚀刻停止层及其形成方法。 在一个实施例中，蚀刻停止层包括拉伸或压缩应力。 在另一个实施例中，在工件的第一区域中形成具有第一厚度并且在工件的第二区域中具有至少一个第二厚度的蚀刻停止层，其中至少一个第二厚度不同于第一厚度。 蚀刻停止层可以在顶表面上比在侧壁表面上更厚。 蚀刻停止层可以在宽间隔的特征区域上更厚，并且在紧密间隔的特征区域上更薄。

公开(公告)号：US07160800B2

公开(公告)日：2007-01-09

申请号：US10905517

申请日：2005-01-07

Applicant: Zhen-Cheng Wu ,  Cheng-Hung Chang ,  Yu-Lien Huang ,  Shwang-Ming Cheng

Inventor： Zhen-Cheng Wu ,  Cheng-Hung Chang ,  Yu-Lien Huang ,  Shwang-Ming Cheng

IPC: H01L21/4763 ,  H01L23/48

CPC classification number: H01L21/76888 ,  H01L21/3003 ,  H01L29/665

Abstract: Disclosed herein are various embodiments of semiconductor devices and related methods of manufacturing a semiconductor device. In one embodiment, a method includes providing a semiconductor substrate and forming a metal silicide on the semiconductor substrate. In addition, the method includes treating an exposed surface of the metal silicide with a hydrogen/nitrogen-containing compound to form a treated layer on the exposed surface, where the composition of the treated layer hinders oxidation of the exposed surface. The method may then further include depositing a dielectric layer over the treated layer and the exposed surface of the metal silicide.

Abstract translation: 这里公开了半导体器件的各种实施例和制造半导体器件的相关方法。 在一个实施例中，一种方法包括提供半导体衬底并在半导体衬底上形成金属硅化物。 此外，该方法包括用含氢/氮化合物处理金属硅化物的暴露表面以在暴露表面上形成处理层，其中处理层的组成阻碍了暴露表面的氧化。 该方法可以进一步包括在经处理的层和金属硅化物的暴露表面上沉积介电层。

公开(公告)号：US09881840B2

公开(公告)日：2018-01-30

申请号：US13157179

申请日：2011-06-09

Applicant: Yu-Lien Huang ,  Ziwei Fang ,  Tsan-Chun Wang ,  Chii-Ming Wu ,  Chun Hsiung Tsai

Inventor： Yu-Lien Huang ,  Ziwei Fang ,  Tsan-Chun Wang ,  Chii-Ming Wu ,  Chun Hsiung Tsai

IPC: H01L21/8238 ,  H01L21/3115 ,  H01L21/033 ,  H01L21/3213

CPC classification number: H01L21/823814 ,  H01L21/0337 ,  H01L21/31155 ,  H01L21/32139 ,  H01L21/823807

Abstract: A hard mask layer with a limited thickness is formed over a gate electrode layer. A treatment is provided on the hard mask layer to transform the hard mask layer to be more resistant to wet etching solution. A patterning is provided on the treated hard mask layer and the gate electrode to from a gate structure.

公开(公告)号：US09263252B2

公开(公告)日：2016-02-16

申请号：US13735949

申请日：2013-01-07

Applicant: Chun-Wei Chang ,  Yi-An Lin ,  Neng-Kuo Chen ,  Sey-Ping Sun ,  Clement Hsingjen Wann ,  Yu-Lien Huang

Inventor： Chun-Wei Chang ,  Yi-An Lin ,  Neng-Kuo Chen ,  Sey-Ping Sun ,  Clement Hsingjen Wann ,  Yu-Lien Huang

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L21/022 ,  H01L29/66545

Abstract: This description relates to a method including forming an interlayer dielectric (ILD) layer and a dummy gate structure over a substrate and forming a cavity in a top portion of the ILD layer. The method further includes forming a protective layer to fill the cavity. The method further includes planarizing the protective layer. A top surface of the planarized protective layer is level with a top surface of the dummy gate structure. This description also relates to a semiconductor device including first and second gate structures and an ILD layer formed on a substrate. The semiconductor device further includes a protective layer formed on the ILD layer, the protective layer having a different etch selectivity than the ILD layer, where a top surface of the protective layer is level with the top surfaces of the first and second gate structures.

Abstract translation: 该描述涉及包括在衬底上形成层间电介质（ILD）层和虚拟栅极结构并在ILD层的顶部形成腔的方法。 该方法还包括形成保护层以填充空腔。 该方法还包括平坦化保护层。 平坦化保护层的顶表面与虚拟栅结构的顶表面平齐。 该描述还涉及包括第一和第二栅极结构以及形成在衬底上的ILD层的半导体器件。 半导体器件还包括形成在ILD层上的保护层，保护层具有与ILD层不同的蚀刻选择性，其中保护层的顶表面与第一和第二栅极结构的顶表面平齐。

公开(公告)号：US20140048855A1

公开(公告)日：2014-02-20

申请号：US13588060

申请日：2012-08-17

Applicant: Yu-Lien Huang ,  Chun-Fu Cheng

Inventor： Yu-Lien Huang ,  Chun-Fu Cheng

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/02118 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device and a method for fabricating the semiconductor device are disclosed. A gate stack is formed over a substrate. A spacer is formed adjoining a sidewall of the gate stack. A recess is formed between the spacer and the substrate. Then, a strained feature is formed in the recess. The disclosed method provides an improved method by providing a space between the spacer and the substrate for forming the strained feature, therefor, to enhance carrier mobility and upgrade the device performance.

Abstract translation: 公开了一种用于制造半导体器件的半导体器件和方法。 栅极叠层形成在衬底上。 形成邻接栅叠层侧壁的间隔物。 在间隔件和基板之间形成凹部。 然后，在凹部中形成应变特征。 所公开的方法通过在间隔物和衬底之间提供形成应变特征的空间来提供改进的方法，从而增强载体移动性并提高装置性能。