公开(公告)号：US08497556B2

公开(公告)日：2013-07-30

申请号：US13607023

申请日：2012-09-07

Applicant: David E. Brown ,  Hans Van Meer ,  Sey-Ping Sun

Inventor： David E. Brown ,  Hans Van Meer ,  Sey-Ping Sun

IPC: H01L31/119

CPC classification number: H01L29/0684 ,  H01L21/84 ,  H01L27/1203

Abstract: A semiconductor product has different active thicknesses of silicon on a single semiconductor substrate. The thickness of the silicon layer is changed either by selectively adding silicon or subtracting silicon from an original layer of silicon. The different active thicknesses are suitable for use in different types of devices, such as diodes and transistors.

Abstract translation: 半导体产品在单个半导体衬底上具有不同的有源厚度的硅。 通过选择性地添加硅或从原始硅层减去硅来改变硅层的厚度。 不同的有源厚度适用于不同类型的器件，例如二极管和晶体管。

公开(公告)号：US20130034948A1

公开(公告)日：2013-02-07

申请号：US13204352

申请日：2011-08-05

Applicant: Gin-Chen Huang ,  Yi-An Lin ,  Ching-Hong Jiang ,  Neng-Kuo Chen ,  Sey-Ping Sun ,  Clement Hsingjen Wann

Inventor： Gin-Chen Huang ,  Yi-An Lin ,  Ching-Hong Jiang ,  Neng-Kuo Chen ,  Sey-Ping Sun ,  Clement Hsingjen Wann

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/3081 ,  H01L21/31053 ,  H01L21/31055

Abstract: A method for fabricating a semiconductor device is disclosed. An exemplary method includes a providing substrate. A dielectric layer is formed over the semiconductor substrate and a stop layer is formed over the dielectric layer. The stop layer and the dielectric layer comprise a different material. The method further includes forming a patterned hard mask layer over the stop layer and etching the semiconductor substrate through the patterned hard mask layer to form a plurality of trenches. The method also includes depositing an isolation material on the semiconductor substrate and substantially filling the plurality of trenches. Thereafter, performing a CMP process on the semiconductor substrate, wherein the CMP process stops on the stop layer.

Abstract translation: 公开了一种制造半导体器件的方法。 一种示例性方法包括提供衬底。 在半导体衬底上形成电介质层，并在电介质层上形成阻挡层。 阻挡层和电介质层包括不同的材料。 该方法还包括在停止层上形成图案化的硬掩模层，并通过图案化的硬掩模层蚀刻半导体衬底以形成多个沟槽。 该方法还包括在半导体衬底上沉积隔离材料并基本上填充多个沟槽。 此后，在半导体衬底上执行CMP处理，其中CMP处理在停止层上停止。

公开(公告)号：US07053400B2

公开(公告)日：2006-05-30

申请号：US10838330

申请日：2004-05-05

Applicant: Sey-Ping Sun ,  David E. Brown

Inventor： Sey-Ping Sun ,  David E. Brown

IPC: H01L31/072

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656

Abstract: The carrier mobility in transistor channel regions of Si—Ge devices is increased by employing a stressed liner. Embodiments include applying a high compressive or tensile stressed film overlying relaxed source/drain regions. Other embodiments include applying a high compressively or high tensilely stressed film, after post silicide spacer removal, over gate electrodes and strained Si source/drain regions of P-channel or N-channel transistors, respectively.

Abstract translation: Si-Ge器件的晶体管沟道区域中的载流子迁移率通过使用应力衬里而增加。 实施例包括施加覆盖松弛的源极/漏极区域的高压缩或拉伸应力膜。 其他实施例包括分别在栅极电极和P沟道或N沟道晶体管的应变Si源极/漏极区之后施加高度压缩或高拉伸应力膜，在硅化物间隔物去除之后。

公开(公告)号：US06265283B1

公开(公告)日：2001-07-24

申请号：US09373217

申请日：1999-08-12

Applicant: Homi E. Nariman ,  Sey-Ping Sun ,  H. Jim Fulford

Inventor： Homi E. Nariman ,  Sey-Ping Sun ,  H. Jim Fulford

IPC: H01L2176

CPC classification number: H01L21/76224

Abstract: Methods of fabricating an isolation structure on a substrate are provided. In one aspect, a method of fabricating an isolation structure on a substrate is provided that includes forming a first insulating layer on the substrate wherein the first insulating layer has a first sidewall. A trench is formed in the substrate that has a second sidewall. A second insulating layer is formed in the trench. The second insulating layer displaces the second sidewall laterally. The first insulating layer is densified by heating to liberate gas therefrom and thereby move the first sidewall into substantial vertical alignment with the second sidewall. The risk of substrate attack due to trench isolation structure pullback is reduced. Trench edges are covered by thick isolation material.

Abstract translation: 提供了在基板上制造隔离结构的方法。 一方面，提供一种在衬底上制造隔离结构的方法，包括在衬底上形成第一绝缘层，其中第一绝缘层具有第一侧壁。 在具有第二侧壁的基板中形成沟槽。 在沟槽中形成第二绝缘层。 第二绝缘层横向移动第二侧壁。 通过加热使第一绝缘层致密化，从而释放出气体，从而使第一侧壁与第二侧壁大致垂直对准。 由于沟槽隔离结构回缩引起的基底侵蚀的风险降低。 沟槽边缘被厚的隔离材料覆盖。

公开(公告)号：US06258730B1

公开(公告)日：2001-07-10

申请号：US09246462

申请日：1999-02-09

Applicant: Sey-Ping Sun ,  Mark I. Gardner ,  Shengnian Song

Inventor： Sey-Ping Sun ,  Mark I. Gardner ,  Shengnian Song

IPC: H01L2131

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/28211 ,  H01L21/31662

Abstract: A fabrication process for semiconductor devices is disclosed for forming ultra-thin gate oxides, whereby a silicon substrate is subjected to an N2O plasma to form the ultra-thin gate oxide. According to one embodiment, the silicon substrate is heated in a deposition chamber and the N2O plasma is created by applying RF power to a showerhead from which the N2O is dispensed. By reacting an N2O plasma directly with the silicon substrate it is possible to achieve gate oxides with thicknesses less than 20 Å and relative uniformities of less than 1% standard deviation. The oxide growth rate resulting from the presently disclosed N2O plasma treatment is much slower than other known oxide formation techniques. One advantage of the disclosed N2O plasma treatment over thermal oxidation lies in the predictability of oxide growth thickness resulting from reaction with N2O plasma versus the strong variation in oxide formation rates exhibited by thermal oxidation. Following gate oxide formation, a high temperature anneal may be performed, preferably in an RTA apparatus. By combining the N2O plasma treatment with an RTA process, the disclosed method is believed to offer a controllable and reproducible method for fabricating highly uniform, ultra-thin gate oxides, having low trapping state densities.

Abstract translation: 公开了用于形成超薄栅极氧化物的半导体器件的制造工艺，由此使硅衬底经受N 2 O等离子体以形成超薄栅极氧化物。 根据一个实施例，在沉积室中加热硅衬底，并且通过将RF功率施加到分配N2O的喷头来产生N 2 O等离子体。 通过使N2O等离子体直接与硅衬底反应，可以实现厚度小于20的栅极氧化物和小于1％标准偏差的相对均匀性。 由本发明的N2O等离子体处理产生的氧化物生长速度比其它已知的氧化物形成技术慢得多。 所公开的N2O等离子体处理对热氧化的一个优点在于与N2O等离子体反应产生的氧化物生长厚度与热氧化显示的氧化物形成速率的强烈变化的可预测性。 在形成栅极氧化物之后，可以优选在RTA装置中进行高温退火。 通过将N2O等离子体处理与RTA工艺结合，所公开的方法被认为是提供具有低陷阱状态密度的制造高度均匀的超薄栅极氧化物的可控和可再现的方法。

公开(公告)号：US06171917B2

公开(公告)日：2001-01-09

申请号：US09048192

申请日：1998-03-25

Applicant: Sey-Ping Sun ,  Thomas E. Spikes ,  Fred N. Hause

Inventor： Sey-Ping Sun ,  Thomas E. Spikes ,  Fred N. Hause

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/31116 ,  H01L21/3185 ,  H01L29/665

Abstract: A method is provided for forming high quality nitride sidewall spacers laterally adjacent to the opposed sidewall surfaces of a gate conductor dielectrically spaced above a semiconductor substrate. In an embodiment, a polysilicon gate conductor is provided which is arranged between a pair of opposed sidewall surfaces upon a gate dielectric. The gate dielectric is arranged upon a semiconductor substrate. Nitride is deposited from a high density plasma source across exposed surfaces of the substrate and the gate conductor. The high density plasma source may be generated within an ECR or ICP reactor containing a gas bearing N2 and SiH4. The energy and flux of electrons, ions, and radicals within the plasma are strictly controlled by the magnetic field such that a substantially stoichiometric and contaminant-free nitride is deposited upon the semiconductor topography. Thereafter, the nitride is anisotropically etched so as to form nitride spacers laterally adjacent the sidewall surfaces of the gate conductor.

Abstract translation: 提供了一种用于在与半导体衬底上介电间隔的栅极导体的相对的侧壁表面横向相邻形成高质量氮化物侧壁间隔件的方法。 在一个实施例中，提供多晶硅栅极导体，其布置在栅极电介质上的一对相对的侧壁表面之间。 栅极电介质被布置在半导体衬底上。 氮化物从高密度等离子体源沉积在衬底和栅极导体的暴露表面上。 高密度等离子体源可以在含有气体N2和SiH4的ECR或ICP反应器内产生。 等离子体中的电子，离子和自由基的能量和通量被磁场严格控制，使得在半导体形貌上沉积基本上化学计量和无污染的氮化物。 此后，各向异性蚀刻氮化物，以便在栅极导体的侧壁表面侧向邻接形成氮化物间隔。

公开(公告)号：US6114219A

公开(公告)日：2000-09-05

申请号：US929865

申请日：1997-09-15

Applicant: Thomas E. Spikes, Jr. ,  Sey-Ping Sun ,  Robert Dawson

Inventor： Thomas E. Spikes, Jr. ,  Sey-Ping Sun ,  Robert Dawson

IPC: H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76224

Abstract: A method for the manufacture of a semiconductor device with trench isolation regions includes forming at least one trench in a substrate to define one or more isolation regions. At least a portion of the trench is filled with a flowable oxide-generating material which is then formed into an oxide layer. An optional dielectric layer can be deposited over the oxide layer. A portion of the oxide layer and/or the optional dielectric layer is removed to generate a substantially planer surface.

Abstract translation: 用于制造具有沟槽隔离区域的半导体器件的方法包括在衬底中形成至少一个沟槽以限定一个或多个隔离区域。 沟槽的至少一部分填充有可流动的氧化物生成材料，然后将其形成为氧化物层。 可以在氧化物层上沉积可选的介电层。 去除氧化物层和/或可选介电层的一部分以产生基本上平的表面。

公开(公告)号：US6051876A

公开(公告)日：2000-04-18

申请号：US2651

申请日：1998-01-05

Applicant: Mark I. Gardner ,  Sey Ping Sun ,  Daniel Kadosh

Inventor： Mark I. Gardner ,  Sey Ping Sun ,  Daniel Kadosh

IPC: H01L23/31 ,  H01L23/48

CPC classification number: H01L23/3171 ,  H01L2924/0002 ,  H01L2924/13091

Abstract: The formation of a graded passivation layer is disclosed. In one embodiment, a method includes four steps. In the first step, at least one transistor on a semiconductor substrate is provided. In the second step, at least one metallization layer is formed over the at least one transistor. In the third step, an oxide layer is deposited over the at least one metallization layer. Finally, in the fourth step, an ion implantation of a predetermined dopant is applied to create a graded passivation film over the at least one metallization layer.

Abstract translation: 公开了渐变钝化层的形成。 在一个实施例中，一种方法包括四个步骤。 在第一步骤中，提供半导体衬底上的至少一个晶体管。 在第二步骤中，在至少一个晶体管上形成至少一个金属化层。 在第三步骤中，氧化物层沉积在至少一个金属化层上。 最后，在第四步骤中，施加预定掺杂剂的离子注入以在至少一个金属化层上产生渐变钝化膜。

公开(公告)号：US08853052B2

公开(公告)日：2014-10-07

申请号：US13204352

申请日：2011-08-05

Applicant: Gin-Chen Huang ,  Yi-An Lin ,  Ching-Hong Jiang ,  Neng-Kuo Chen ,  Sey-Ping Sun ,  Clement Hsingjen Wann

Inventor： Gin-Chen Huang ,  Yi-An Lin ,  Ching-Hong Jiang ,  Neng-Kuo Chen ,  Sey-Ping Sun ,  Clement Hsingjen Wann

IPC: H01L21/76 ,  H01L29/00 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/3081 ,  H01L21/31053 ,  H01L21/31055

Abstract: A method for fabricating a semiconductor device is disclosed. An exemplary method includes a providing substrate. A dielectric layer is formed over the semiconductor substrate and a stop layer is formed over the dielectric layer. The stop layer and the dielectric layer comprise a different material. The method further includes forming a patterned hard mask layer over the stop layer and etching the semiconductor substrate through the patterned hard mask layer to form a plurality of trenches. The method also includes depositing an isolation material on the semiconductor substrate and substantially filling the plurality of trenches. Thereafter, performing a CMP process on the semiconductor substrate, wherein the CMP process stops on the stop layer.

Abstract translation: 公开了一种制造半导体器件的方法。 一种示例性方法包括提供衬底。 在半导体衬底上形成电介质层，并在电介质层上形成阻挡层。 阻挡层和电介质层包括不同的材料。 该方法还包括在停止层上形成图案化的硬掩模层，并通过图案化的硬掩模层蚀刻半导体衬底以形成多个沟槽。 该方法还包括在半导体衬底上沉积隔离材料并基本上填充多个沟槽。 此后，在半导体衬底上执行CMP处理，其中CMP处理在停止层上停止。

公开(公告)号：US08507996B2

公开(公告)日：2013-08-13

申请号：US12789046

申请日：2010-05-27

Applicant: Sey-Ping Sun ,  Chih-Hao Chang ,  Chao-An Jong ,  Tsung-Lin Lee ,  Chung-Ju Lee ,  Chin-Hsiang Lin

Inventor： Sey-Ping Sun ,  Chih-Hao Chang ,  Chao-An Jong ,  Tsung-Lin Lee ,  Chung-Ju Lee ,  Chin-Hsiang Lin

IPC: H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/76804 ,  H01L21/76816 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit structure includes a semiconductor substrate; a gate stack overlying the semiconductor substrate; a gate spacer on a sidewall of the gate stack; a first contact plug having an inner edge contacting a sidewall of the gate spacer, and a top surface level with a top surface of the gate stack; and a second contact plug over and contacting the first contact plug. The second contact plug has a cross-sectional area smaller than a cross-sectional area of the first contact plug.

Abstract translation: 集成电路结构包括半导体衬底; 覆盖半导体衬底的栅极堆叠; 在栅极堆叠的侧壁上的栅极间隔物; 具有接触所述栅极隔离物的侧壁的内边缘的第一接触插塞和具有所述栅极堆叠的顶表面的顶表面水平; 以及第二接触插头，并且与第一接触插塞接触。 第二接触插塞的横截面积小于第一接触插塞的横截面面积。