公开(公告)号：US08742504B2

公开(公告)日：2014-06-03

申请号：US13891636

申请日：2013-05-10

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Pranita Kerber ,  Ghavam G. Shahidi

IPC: H01L27/12

CPC classification number: H01L29/786 ,  H01L29/66772 ,  H01L29/78654 ,  H01L29/78696

Abstract: A semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes a semiconductor substrate, an insulating layer, a first semiconductor layer, a dielectric layer, a second semiconductor layer, a source and drain junction, a gate, and a spacer. The method includes the steps of forming a semiconductor substrate, forming a shallow trench isolation layer, growing a first epitaxial layer, growing a second epitaxial layer, forming a gate, forming a spacer, performing a reactive ion etching, removing a portion of the first epitaxial layer, filling the void with a dielectric, etching back a portion of the dielectric, growing a silicon layer, implanting a source and drain junction, and forming an extension.

Abstract translation: 半导体器件和半导体器件的制造方法。 半导体器件包括半导体衬底，绝缘层，第一半导体层，电介质层，第二半导体层，源极和漏极结，栅极和间隔物。 该方法包括以下步骤：形成半导体衬底，形成浅沟槽隔离层，生长第一外延层，生长第二外延层，形成栅极，形成间隔物，执行反应离子蚀刻，去除第一 外延层，用电介质填充空隙，蚀刻电介质的一部分，生长硅层，注入源极和漏极结，以及形成延伸。

公开(公告)号：US20140145246A1

公开(公告)日：2014-05-29

申请号：US14167499

申请日：2014-01-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tak H. Ning ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kerber

IPC: H01L29/812 ,  H01L29/66 ,  H01L29/78 ,  H01L29/808

CPC classification number: H01L29/812 ,  H01L21/84 ,  H01L21/845 ,  H01L27/098 ,  H01L27/1203 ,  H01L29/66545 ,  H01L29/66848 ,  H01L29/66893 ,  H01L29/785 ,  H01L29/808

Abstract: A method of fabricating a semiconductor device that includes forming a replacement gate structure on a portion of a semiconductor substrate, wherein source regions and drain regions are formed in opposing sides of the replacement gate structure. A dielectric is formed on the semiconductor substrate having an upper surface that is coplanar with an upper surface of the replacement gate structure. The replacement gate structure is removed to provide an opening to an exposed portion of the semiconductor substrate. A functional gate conductor is epitaxially grown within the opening in direct contact with the exposed portion of the semiconductor substrate. The method is applicable to planar metal oxide semiconductor field effect transistors (MOSFETs) and fin field effect transistors (finFETs).

Abstract translation: 一种制造半导体器件的方法，包括在半导体衬底的一部分上形成替换栅极结构，其中源极区和漏极区形成在替换栅极结构的相对侧。 在具有与替换栅极结构的上表面共面的上表面的半导体衬底上形成电介质。 去除替代栅极结构以提供对半导体衬底的暴露部分的开口。 功能栅极导体在开口内外延生长，与半导体衬底的暴露部分直接接触。 该方法适用于平面金属氧化物半导体场效应晶体管（MOSFET）和鳍式场效应晶体管（finFET）。

公开(公告)号：US20140124862A1

公开(公告)日：2014-05-08

申请号：US14154438

申请日：2014-01-14

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Pranita Kerber ,  Ali Khakifirooz ,  Balasubramanian Pranatharthiharan

IPC: H01L29/06

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L21/84 ,  H01L29/66545

Abstract: A structure to improve ETSOI MOSFET devices includes a wafer having regions with at least a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer. The regions are separated by a STI which extends at least partially into the second semiconductor layer and is partially filled with a dielectric. A gate structure is formed over the first semiconductor layer and during the wet cleans involved, the STI divot erodes until it is at a level below the oxide layer. Another dielectric layer is deposited over the device and a hole is etched to reach source and drain regions. The hole is not fully landed, extending at least partially into the STI, and an insulating material is deposited in the hole.

Abstract translation: 改进ETSOI MOSFET器件的结构包括具有至少覆盖在第二半导体层上的氧化物层上的第一半导体层的区域的晶片。 这些区域由至少部分地延伸到第二半导体层中并且部分地填充有电介质的STI分开。 栅极结构形成在第一半导体层之上，并且在涉及的湿清洗期间，STI纹理腐蚀直到其处于低于氧化物层的水平。 在器件上沉积另一个介电层，并蚀刻一个孔以到达源极和漏极区。 孔没有完全着陆，至少部分地延伸到STI中，并且绝缘材料沉积在孔中。

公开(公告)号：US20140042542A1

公开(公告)日：2014-02-13

申请号：US14059871

申请日：2013-10-22

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Pranita Kerber ,  Ali Khakifirooz

IPC: H01L29/78

CPC classification number: H01L29/0603 ,  H01L29/1054 ,  H01L29/4236 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/78

Abstract: MOSFETs and methods for making MOSFETs with a recessed channel and abrupt junctions are disclosed. The method includes creating source and drain extensions while a dummy gate is in place. The source/drain extensions create a diffuse junction with the silicon substrate. The method continues by removing the dummy gate and etching a recess in the silicon substrate. The recess intersects at least a portion of the source and drain junction. Then a channel is formed by growing a silicon film to at least partially fill the recess. The channel has sharp junctions with the source and drains, while the unetched silicon remaining below the channel has diffuse junctions with the source and drain. Thus, a MOSFET with two junction regions, sharp and diffuse, in the same transistor can be created.

公开(公告)号：US20130240998A1

公开(公告)日：2013-09-19

申请号：US13870220

申请日：2013-04-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Pranita Kerber ,  Ali Khakifirooz ,  Ghavam G. Shahidi

IPC: H01L27/07

CPC classification number: H01L27/0727 ,  H01L21/823418 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203

Abstract: A method includes forming isolation regions in a semiconductor substrate to define a first field effect transistor (FET) region, a second FET region, and a diode region, forming a first gate stack in the first FET region and a second gate stack in the second FET region, forming a layer of spacer material over the second FET region and the second gate stack, forming a first source region and a first drain region in the first FET region and a first diode layer in the diode region using a first epitaxial growth process, forming a hardmask layer over the first source region, the first drain region, the first gate stack and a portion of the first diode layer, and forming a second source region and a second drain region in the first FET region and a second diode layer on the first diode layer using a second epitaxial growth process.

Abstract translation: 一种方法包括在半导体衬底中形成隔离区以限定第一场效应晶体管（FET）区域，第二FET区域和二极管区域，在第一FET区域中形成第一栅极堆叠，在第二FET区域中形成第二栅极堆叠 FET区域，在所述第二FET区域和所述第二栅极堆叠上形成间隔材料层，在所述第一FET区域中形成第一源极区域和第一漏极区域，以及使用第一外延生长工艺在所述二极管区域中形成第一二极管层 在所述第一源极区域，所述第一漏极区域，所述第一栅极堆叠层和所述第一二极管层的一部分上形成硬掩模层，以及在所述第一FET区域中形成第二源极区域和第二漏极区域，以及在所述第一FET区域中形成第二二极管层 使用第二外延生长工艺在第一二极管层上。

公开(公告)号：US10217745B2

公开(公告)日：2019-02-26

申请号：US15959832

申请日：2018-04-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Martin M. Frank ,  Pranita Kerber ,  Vijay Narayanan

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L21/8238 ,  H01L29/49 ,  H01L21/8258 ,  H01L21/28

Abstract: An electrical device that includes at least one n-type field effect transistor including a channel region in a type III-V semiconductor device, and at least one p-type field effect transistor including a channel region in a germanium containing semiconductor material. Each of the n-type and p-type semiconductor devices may include gate structures composed of material layers including work function adjusting materials selections, such as metal and doped dielectric layers. The field effect transistors may be composed of fin type field effect transistors. The field effect transistors may be formed using gate first processing or gate last processing.

公开(公告)号：US10176990B2

公开(公告)日：2019-01-08

申请号：US15241287

申请日：2016-08-19

Applicant: International Business Machines Corporation

Inventor： Pranita Kerber ,  Qiqing C. Ouyang ,  Alexander Reznicek

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/306 ,  H01L29/78 ,  H01L29/165 ,  H01L21/285 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/161

Abstract: A semiconductor device and a method for fabricating the device. The method includes: providing a FinFET having a source/drain region, at least one SiGe fin, a silicon substrate, a local oxide layer is formed on the silicon substrate, a gate structure is formed on the at least one SiGe fin and the local oxide layer, the gate structure is encapsulated by a gate hard mask and sidewall spacer layers; recessing the at least one SiGe fin in the source/drain region to the sidewall spacer layers and the silicon substrate layer; recessing the local oxide layer in the source/drain region to the sidewall spacer layer and the silicon substrate; growing a n-doped silicon layer on the silicon substrate; growing a p-doped silicon layer or p-doped SiGe layer on the n-doped silicon layer; and forming a silicide layer on the p-doped silicon layer or p-doped SiGe layer.

公开(公告)号：US09773903B2

公开(公告)日：2017-09-26

申请号：US15377722

申请日：2016-12-13

Applicant: International Business Machines Corporation

Inventor： Cheng-Wei Cheng ,  Pranita Kerber ,  Effendi Leobandung ,  Amlan Majumdar ,  Renee T. Mo ,  Yanning Sun

IPC: H01L29/78 ,  H01L23/535 ,  H01L29/06 ,  H01L29/32 ,  H01L29/66 ,  H01L21/311 ,  H01L29/778

CPC classification number: H01L29/7835 ,  H01L21/2258 ,  H01L21/31105 ,  H01L21/31116 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/32 ,  H01L29/66462 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure containing a high mobility semiconductor channel material, i.e., a III-V semiconductor material, and asymmetrical source/drain regions located on the sidewalls of the high mobility semiconductor channel material is provided. The asymmetrical source/drain regions can aid in improving performance of the resultant device. The source region contains a source-side epitaxial doped semiconductor material, while the drain region contains a drain-side epitaxial doped semiconductor material and an underlying portion of the high mobility semiconductor channel material.

公开(公告)号：US09741807B2

公开(公告)日：2017-08-22

申请号：US15359929

申请日：2016-11-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Keith E. Fogel ,  Pranita Kerber ,  Qiqing C. Ouyang ,  Alexander Reznicek

IPC: H01L29/76 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/285 ,  H01L21/768 ,  H01L23/535 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L27/088 ,  H01L29/45

CPC classification number: H01L29/41791 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76895 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a semiconductor device that includes forming a fin structure from a semiconductor substrate, and forming a gate structure on a channel region portion of the fin structure. A source region and a drain region are formed on a source region portion and a drain region portion of the fin structure on opposing sides of the channel portion of the fin structure. At least one sidewall of the source region portion and the drain region portion of the fin structure is exposed. A metal semiconductor alloy is formed on the at least one sidewall of the source region portion and the drain region portion of the fin structure that is exposed.

公开(公告)号：US09722031B2

公开(公告)日：2017-08-01

申请号：US15146148

申请日：2016-05-04

Applicant: International Business Machines Corporation

Inventor： Cheng-Wei Cheng ,  Pranita Kerber ,  Young-Hee Kim ,  Effendi Leobandung ,  Yanning Sun

IPC: H01L29/20 ,  H01L29/10 ,  H01L29/12 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/306 ,  H01L21/02 ,  H01L29/207 ,  H01L21/8252 ,  H01L29/08 ,  H01L29/66 ,  H01L29/205

CPC classification number: H01L29/20 ,  H01L21/02392 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/0257 ,  H01L21/30612 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/8252 ,  H01L29/0603 ,  H01L29/0607 ,  H01L29/0657 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1041 ,  H01L29/1054 ,  H01L29/12 ,  H01L29/205 ,  H01L29/207 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7833

Abstract: A method for fabricating a semiconductor device may include receiving a gated substrate comprising a substrate with a channel layer and a gate structure formed thereon, over-etching the channel layer to expose an extension region below the gate structure, epitaxially growing a halo layer on the exposed extension region using a first in-situ dopant and epitaxially growing a source or drain on the halo layer using a second in-situ dopant, wherein the first in-situ dopant and the second in-situ dopant are of opposite doping polarity. Using an opposite doping polarity may provide an energy band barrier for the semiconductor device and reduce leakage current. A corresponding apparatus is also disclosed herein.