-
公开(公告)号：US11916130B2
公开(公告)日：2024-02-27
申请号：US17186533
申请日：2021-02-26
发明人： Kuen-Ting Shiu , Tak H. Ning , Jeng-Bang Yau , Cheng-Wei Cheng , Ko-Tao Lee
IPC分类号： H01L29/66 , H01L29/737 , H01L21/308 , H01L29/06 , H01L21/306 , H01L29/205
CPC分类号： H01L29/66318 , H01L21/308 , H01L21/30621 , H01L29/0649 , H01L29/205 , H01L29/737
摘要： A lateral bipolar junction transistor including an emitter region, base region and collector region laterally orientated over a type IV semiconductor substrate, each of the emitter region, the base region and the collector region being composed of a type III-V semiconductor material. A buried oxide layer is present between the type IV semiconductor substrate and the emitter region, the base region and the collector region. The buried oxide layer having a pedestal aligned with the base region.
-
公开(公告)号：US11444185B2
公开(公告)日：2022-09-13
申请号：US16661518
申请日：2019-10-23
IPC分类号： H01L29/737 , H01L29/06 , H01L29/66 , H01L21/306 , H01L29/205 , H01L21/762
摘要： A bipolar junction transistor (LBJT) device that includes a base region of a first III-V semiconductor material having A first band gap; and emitter and collector regions present on opposing sides of the base region, wherein the emitter and collector regions are comprised of a second III-V semiconductor material having a wider band gap than the first III-V semiconductor material. A dielectric region is present underlying the base region, emitter region and the collect region. The dielectric region has an inverted apex geometry. The sidewalls of dielectric region that extend to the apex of the inverted apex geometry are present on facets of a supporting substrate III-V semiconductor material having a {110} crystalline orientation.
-
公开(公告)号：US11355553B2
公开(公告)日：2022-06-07
申请号：US16704245
申请日：2019-12-05
IPC分类号： H01L27/24 , H01L29/786 , H01L29/66 , H01L45/00
摘要： A semiconductor structure may include a vertical field effect transistor, the vertical field effect transistor may include a top source drain, a bottom source drain, and an epitaxial channel and a resistive random access memory below the vertical field effect transistor. The resistive random access memory may include an epitaxial oxide layer, a top electrode, and a bottom electrode. The top electrode, which may function as the bottom source drain of the vertical field effect transistor, may be in direct contact with the epitaxial channel of the vertical field effect transistor. The epitaxial oxide layer may separate the top electrode from the bottom electrode. The top source drain may be arranged between a dielectric material and the epitaxial channel. The dielectric material may be in direct contact with a top surface of the epitaxial channel. The epitaxial oxide layer may be composed of a rare earth oxide.
-
公开(公告)号：US10964709B2
公开(公告)日：2021-03-30
申请号：US16352222
申请日：2019-03-13
IPC分类号： H01L27/11521 , H01L27/11568 , H01L27/112 , H01L27/092 , H01L29/78 , H01L27/06 , H01L27/12 , G11C16/04 , H01L27/11551 , H01L29/788
摘要： A method for integrating a stack of fins to form an electrically erasable programmable read-only memory (EEPROM) device is presented. The method includes forming a stack of at least a first fin structure and a second fin structure over a semiconductor substrate, forming a sacrificial gate straddling the stack of at least the first fin structure and the second fin structure, forming a first conductivity type source/drain region to the first fin structure, and forming a second conductivity type source/drain to the second fin structure. The method further includes removing the sacrificial gate to form a gate opening, and forming a single floating gate in communication with a channel for each of the first and second fin structures.
-
公开(公告)号：US10916651B2
公开(公告)日：2021-02-09
申请号：US16794473
申请日：2020-02-19
IPC分类号： H01L29/78 , H01L29/66 , H01L21/28 , H01L21/311 , H01L29/423
摘要： A method for forming the semiconductor device that includes forming a gate opening to a channel region of a fin structure; and forming a dielectric layer on the fin structure, in which an upper portion of the fin structure is exposed. A metal is formed within the gate opening. The portions of the metal directly contacting the upper surface of fin structure provide a body contact. The combination of the metal within the gate opening to the channel region of the fin structure and the dielectric layer provide a functional gate structure to the semiconductor device.
-
公开(公告)号：US10916629B2
公开(公告)日：2021-02-09
申请号：US16050810
申请日：2018-07-31
IPC分类号： H01L29/10 , H01L21/8238 , H01L29/792 , H01L27/11568 , H01L29/66 , H01L27/092 , H01L29/06
摘要： A semiconductor structure that occupies only one areal device area is provided that includes a charge storage region sandwiched between a pFET nanosheet device and an nFET nanosheet device. The charge storage region is an epitaxial oxide nanosheet that is lattice matched to an underlying first silicon channel material nanosheet and an overlying second silicon channel material nanosheet. The semiconductor structure can be used as an EPROM device.
-
公开(公告)号：US20200273967A1
公开(公告)日：2020-08-27
申请号：US16284422
申请日：2019-02-25
摘要： A method for manufacturing a semiconductor device includes forming a fin on a semiconductor substrate, and forming a bottom source/drain region adjacent a base of the fin. In the method, a dielectric layer, a work function metal layer and a first gate metal layer are sequentially deposited on the bottom source/drain region and around the fin. The dielectric layer, the work function metal layer and the first gate metal layer form a gate structure. The method also includes removing the dielectric layer, the work function metal layer and the first gate metal layer from an end portion of the fin, and depositing a second gate metal layer around the end portion of fin in place of the removed dielectric layer, the removed work function metal layer and the removed first gate metal layer. The second gate metal layer contacts the end portion of the fin.
-
公开(公告)号：US10727299B2
公开(公告)日：2020-07-28
申请号：US16149598
申请日：2018-10-02
发明人： Kevin K. Chan , Pouya Hashemi , Tak H. Ning , Alexander Reznicek
IPC分类号： H01L29/08 , H01L29/735 , H01L23/31 , H01L29/161 , H01L29/20 , H01L29/10 , H01L29/737 , H01L29/165 , H01L29/04 , H01L29/06 , H01L23/29 , H01L29/66 , H01L21/683 , H01L21/02 , H01L21/308 , H01L21/265 , H01L21/74
摘要： A lateral bipolar junction transistor (LBJT) device that may include a dielectric stack including a pedestal of a base region passivating dielectric and a nucleation dielectric layer; and a base region composed of a germanium containing material or a type III-V semiconductor material in contact with the pedestal of the base region passivating dielectric. An emitter region and collector region may be present on opposing sides of the base region contacting a sidewall of the pedestal of the base region passivating dielectric and an upper surface of the nucleation dielectric layer.
-
9.发明申请公开(公告)号：US20200066874A1
公开(公告)日：2020-02-27
申请号：US16671844
申请日：2019-11-01
IPC分类号： H01L29/66 , H01L29/423 , H01L29/78 , H01L29/08 , H01L29/06 , H01L27/11521
摘要： A vertically stacked set of an n-type vertical transport field effect transistor (n-type VT FET) and a p-type vertical transport field effect transistor (p-type VT FET) is provided. The vertically stacked set of the n-type VT FET and the p-type VT FET includes a first bottom source/drain layer on a substrate, that has a first conductivity type, a lower channel pillar on the first bottom source/drain layer, and a first top source/drain on the lower channel pillar, that has the first conductivity type. The vertically stacked set of the n-type VT FET and the p-type VT FET further includes a second bottom source/drain on the first top source/drain, that has a second conductivity type different from the first conductivity type, an upper channel pillar on the second bottom source/drain, and a second top source/drain on the upper channel pillar, that has the second conductivity type.
-
公开(公告)号：US20190326397A1
公开(公告)日：2019-10-24
申请号：US16502271
申请日：2019-07-03
发明人： Kevin K. Chan , Pouya Hashemi , Tak H. Ning , Alexander Reznicek
IPC分类号： H01L29/08 , H01L21/265 , H01L29/06 , H01L29/161 , H01L21/308 , H01L21/02 , H01L21/683 , H01L29/66 , H01L23/29 , H01L29/165 , H01L29/737 , H01L29/10 , H01L29/20 , H01L23/31 , H01L29/735 , H01L29/04
摘要： A lateral bipolar junction transistor (LBJT) device that may include a dielectric stack including a pedestal of a base region passivating dielectric and a nucleation dielectric layer; and a base region composed of a germanium containing material or a type III-V semiconductor material in contact with the pedestal of the base region passivating dielectric. An emitter region and collector region may be present on opposing sides of the base region contacting a sidewall of the pedestal of the base region passivating dielectric and an upper surface of the nucleation dielectric layer.
-
-
-
-
-
-
-
-
-
搜索结果
285 条记录 (耗时 0.032 秒)
