公开(公告)号：US20180158771A1

公开(公告)日：2018-06-07

申请号：US15721784

申请日：2017-09-30

申请人： Renesas Electronics Corporation

发明人： Toshihiko AKIBA ,  Shuuichi KARIYAZAKI

IPC分类号： H01L23/528 ,  H01L23/15 ,  H01L23/00

CPC分类号： H01L23/528 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/17 ,  H01L24/49 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/4901 ,  H01L2224/494 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311

摘要： It is intended to reduce the price of a semiconductor device and increase the reliability thereof. In an interposer, a plurality of wiring layers are disposed between uppermost-layer wiring and lowermost-layer wiring. For example, a third wiring layer is electrically coupled directly to a first wiring layer as the uppermost-layer wiring by a long via wire extending through insulating layers without intervention of a second wiring layer. For example, an upper-surface terminal made of the first wiring layer is electrically coupled directly to a via land made of the third wiring layer by the long via wire. Between the adjacent long via wires, three lead-out wires made of the second wiring layer can be placed. The number of the lead-out wires that can be placed between the adjacent long via wires is larger than the number of the lead-out wires that can be placed between the adjacent via lands.

公开(公告)号：US09984947B2

公开(公告)日：2018-05-29

申请号：US15670589

申请日：2017-08-07

申请人： Amkor Technology, Inc.

发明人： Ji Young Chung ,  Dong Joo Park ,  Jin Seong Kim ,  Jae Sung Park ,  Se Hwan Hong

IPC分类号： G06K9/00 ,  H01L23/15 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498 ,  H01L23/495

CPC分类号： H01L23/15 ,  G06K9/00053 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/4952 ,  H01L23/49805 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/02166 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48165 ,  H01L2224/48227 ,  H01L2224/48992 ,  H01L2224/48997 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00015 ,  H01L2924/00012

摘要： A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various fingerprint sensor devices, and methods of manufacturing thereof, that comprise an interconnection structure, for example a bond wire, at least a portion of which extends into a dielectric layer utilized to mount a plate, and/or that comprise an interconnection structure that extends upward from the semiconductor die at a location that is laterally offset from the plate.

公开(公告)号：US20180145004A1

公开(公告)日：2018-05-24

申请号：US15574230

申请日：2016-05-11

申请人： SONY CORPORATION

发明人： Kousuke SEKI ,  Yusaku KATO ,  Shun MITARAI ,  Shinji ROKUHARA

IPC分类号： H01L23/15 ,  H01L23/32 ,  H01L23/36 ,  H05K1/11 ,  H05K1/05 ,  H05K3/44 ,  H05K3/42

CPC分类号： H01L23/15 ,  H01L21/486 ,  H01L23/32 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/5384 ,  H01L23/5389 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/16225 ,  H05K1/056 ,  H05K1/09 ,  H05K1/095 ,  H05K1/11 ,  H05K1/115 ,  H05K3/4061 ,  H05K3/426 ,  H05K3/445 ,  H05K2201/026 ,  H05K2201/0323 ,  H05K2201/068 ,  H05K2201/0959

摘要： The present disclosure relates to a wiring board and a manufacturing method that simultaneously solve problems of stress and heat release A wiring board as one aspect of the present disclosure includes a glass substrate as a core member, and a plurality of through holes arranged in a cyclic manner in the glass substrate. The through holes are filled with different kinds of filling materials. A wiring board manufacturing method as one aspect of the present disclosure includes: a through hole formation step of forming through holes arranged in a cyclic manner in a glass substrate serving as a core member; and a filling step of forming a protecting sheet on the glass substrate, and filling through holes with a filling material through openings formed in the protecting sheet. The present disclosure can be applied to a wiring board that has a through-electrode-equipped glass substrate as the core member.

公开(公告)号：US20180122791A1

公开(公告)日：2018-05-03

申请号：US15859097

申请日：2017-12-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Chih Liu ,  Kuan-Lin Ho ,  Wei-Ting Lin ,  Chin-Liang Chen ,  Jing Ruei Lu

IPC分类号： H01L25/00 ,  H01L25/065

CPC分类号： H01L25/50 ,  H01L21/561 ,  H01L21/565 ,  H01L23/145 ,  H01L23/15 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/49811 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/08225 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/80 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/01029 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/01047

摘要： Embodiments relate to packages and methods of forming packages. A package includes a package substrate, a first device die, first electrical connectors, an encapsulant, a redistribution structure, and a second device die. The first device die is attached to a side of the package substrate, and the first electrical connectors are mechanically and electrically coupled to the side of the package substrate. The encapsulant at least laterally encapsulates the first electrical connectors and the first device die. The redistribution structure is on the encapsulant and the first electrical connectors. The redistribution structure is directly coupled to the first electrical connectors. The first device die is disposed between the redistribution structure and the package substrate. The second device die is attached to the redistribution structure by second electrical connectors, and the second electrical connectors are directly coupled to the redistribution structure.

公开(公告)号：US09960120B2

公开(公告)日：2018-05-01

申请号：US15083926

申请日：2016-03-29

申请人： SHINKO ELECTRIC INDUSTRIES CO., LTD.

发明人： Ryo Fukasawa ,  Sumihiro Ichikawa ,  Michio Horiuchi

IPC分类号： H01L23/538 ,  H01L23/498 ,  H01L23/15 ,  H01L23/14 ,  H01L23/544 ,  H01L23/367 ,  H01L25/065

CPC分类号： H01L23/5385 ,  H01L23/145 ,  H01L23/15 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/538 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5387 ,  H01L23/544 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2224/08113 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16141 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32141 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06506 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/15311 ,  H01L2924/15321

摘要： A wiring substrate includes a buried substrate disposed within a through-hole penetrating through a resin substrate of a core layer and including a plate-like body and a plurality of linear conductors penetrating the plate-like body, a first insulating layer covering a first surface of the resin substrate, a first wiring layer including a first pad pattern formed on a first surface of the buried substrate and a first wiring pattern formed on a first surface of the first insulating layer, and a third wiring pattern formed on the first surface of the resin substrate and covered by the first insulating layer. In the plurality of linear conductors, a gap between the adjacent linear conductors is smaller than a diameter of each of the linear conductors. The third wiring pattern is formed so as to have a thickness thicker than a thickness of the first wiring pattern.

公开(公告)号：US09913405B2

公开(公告)日：2018-03-06

申请号：US14668017

申请日：2015-03-25

申请人： International Business Machines Corporation

发明人： Jeffrey P. Gambino ,  Richard S. Graf ,  Sudeep Mandal ,  David J. Russell

IPC分类号： H01L21/00 ,  H05K7/20 ,  H01L35/34 ,  H01L23/15 ,  H01L23/38 ,  H05K1/03 ,  H01L23/13 ,  H01L23/00

CPC分类号： H05K7/2039 ,  H01L23/13 ,  H01L23/15 ,  H01L23/38 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L35/34 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/181 ,  H05K1/0306 ,  H05K2201/10219 ,  H05K2201/10378 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012

摘要： The present invention relates generally to integrated circuit (IC) chip packaging, and more particularly, to a structure and method of forming a glass interposer having one or more embedded peltier devices, alongside electrically conductive vias, to help dissipate heat from one or more IC chips in a multi-dimensional chip package through the glass interposer and into an organic carrier, where it can be dissipated into an underlying substrate.

公开(公告)号：US20180061817A1

公开(公告)日：2018-03-01

申请号：US15802525

申请日：2017-11-03

申请人： International Business Machines Corporation ,  STMicroelectronics, Inc.

发明人： Lawrence A. Clevenger ,  Carl J. Radens ,  Yiheng Xu ,  John H. Zhang

IPC分类号： H01L25/18 ,  H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L21/48 ,  H01L23/538

CPC分类号： H01L25/18 ,  H01L21/4846 ,  H01L23/13 ,  H01L23/15 ,  H01L23/3107 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5389 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15156 ,  H01L2924/15313 ,  H01L2924/157

摘要： Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by the first stair, wherein the at least one additional chip is vertically spaced apart from the first chip.

公开(公告)号：US20180033742A1

公开(公告)日：2018-02-01

申请号：US15220221

申请日：2016-07-26

申请人： Palo Alto Research Center Incorporated

发明人： Christopher L. Chua ,  Jeng Ping Lu ,  Gregory Whiting ,  Scott J. Limb ,  Rene A. Lujan ,  Qian Wang

IPC分类号： H01L23/00 ,  H01L23/525 ,  H01L31/20 ,  H01L23/34 ,  H01L23/15 ,  H01L23/64

CPC分类号： H01L23/576 ,  H01L23/15 ,  H01L23/345 ,  H01L23/5256 ,  H01L23/57 ,  H01L23/64 ,  H01L29/74 ,  H01L31/022408 ,  H01L31/022475 ,  H01L31/202 ,  H03K19/17768

摘要： A self-destructing device includes a stressed substrate with a heater thermally coupled to the stressed substrate. The device includes a power source and trigger circuitry comprising a sensor and a switch. The sensor generates a trigger signal when exposed to a trigger stimulus. The switch couples the power source to the heater in response to the trigger signal When energized by the power source, the heater generates heat sufficient to initiate self-destruction of the stressed substrate.

公开(公告)号：US20180027649A1

公开(公告)日：2018-01-25

申请号：US15718507

申请日：2017-09-28

申请人： TAI-SAW Technology Co., Ltd.

发明人： Yu-Tung Huang ,  Ming-Hung Chang ,  Szu-Heng Liu ,  You-Jen Cho

IPC分类号： H05K1/02 ,  G01N33/487 ,  G01N31/00 ,  H05K3/10 ,  G01N33/18

CPC分类号： H05K1/0272 ,  G01N31/00 ,  G01N33/18 ,  G01N33/48707 ,  H01L23/15 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/1319 ,  H01L2224/16237 ,  H01L2224/81192 ,  H01L2224/81385 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H05K1/111 ,  H05K3/10 ,  H05K3/305 ,  H05K2201/0302 ,  H05K2201/0373 ,  H05K2201/09781 ,  Y02P70/613 ,  Y10T156/10 ,  H01L2924/00014

摘要： A strip for an electronic device senses a liquid sample. The strip includes a substrate having a first surface, a plurality of protrusions disposed on the first surface, and each having a width, and a hydrophilic layer having a layer surface disposed on the first surface and the plurality of protrusions, and having a second surface opposite to the layer surface, whereby the liquid sample and the second surface have a contact angle therebetween ranging from 2 to 85 degrees when the liquid sample is disposed on the hydrophilic layer.

公开(公告)号：US09861313B1

公开(公告)日：2018-01-09

申请号：US15214942

申请日：2016-07-20

申请人： International Business Machines Corporation

发明人： John U. Knickerbocker ,  Shriya Kumar ,  Jae-Woong Nah

IPC分类号： H01L41/113 ,  A61B5/00 ,  B23K3/06 ,  A61M5/00 ,  B23K101/36

CPC分类号： A61B5/68 ,  A61B2562/12 ,  A61M5/00 ,  A61M2207/00 ,  B23K3/0638 ,  B23K2101/36 ,  H01L21/486 ,  H01L21/76816 ,  H01L21/76852 ,  H01L21/76883 ,  H01L21/76898 ,  H01L23/15 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/32 ,  H01L24/64 ,  H01L24/69 ,  H01L24/83 ,  H01L24/89 ,  H01L2223/6677 ,  H01L2224/27312 ,  H01L2224/32111 ,  H01L2224/32235 ,  H01L2224/325 ,  H01L2224/64 ,  H01L2224/69 ,  H01L2224/83801 ,  H01L2224/89 ,  H01L2224/96 ,  H01L2924/014 ,  H01L2924/1434 ,  H01L2924/15332 ,  H05K1/0306 ,  H05K3/4038 ,  H05K2201/0305

摘要： A method includes forming one or more trenches in a first substrate, forming one or more vias in a second substrate, aligning at least a first trench in the first substrate with at least a first via in the second substrate, and sealing the first substrate to the second substrate by filling the first via and the first trench with solder material using injection molded soldering.