公开(公告)号：US11816337B2

公开(公告)日：2023-11-14

申请号：US17543473

申请日：2021-12-06

Applicant: Western Digital Technologies, Inc.

Inventor： Judah Gamliel Hahn ,  Avichay Haim Hodes ,  Shay Benisty ,  Michael James

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F3/0616 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0688 ,  G06F13/1673 ,  G06F13/4022 ,  G06F13/4221 ,  G06F2213/0026

Abstract: A storage system includes one or more data storage devices, a PCIe switch coupled to the one or more data storage devices, and a controller unit coupled to the PCIe switch. The controller unit includes a dynamic random access memory (DRAM) host memory buffer (HMB) controller and a DRAM pool or a controller memory buffer (CMB) controller, a root complex/port, and the DRAM pool. The DRAM pool includes one or more DRAM devices. The one or more data storage devices are configured to interact with the controller unit and store data to a DRAM of the DRAM pool of the controller unit.

公开(公告)号：US20230359578A1

公开(公告)日：2023-11-09

申请号：US18131185

申请日：2023-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghan LEE ,  Jae-gon LEE ,  Chon Yong LEE

IPC: G06F13/42 ,  G06F13/16 ,  G06F12/02

CPC classification number: G06F13/4221 ,  G06F13/1668 ,  G06F12/0238

Abstract: A computing system includes a first storage device, a second storage device, a memory device, and a compute express link (CXL) switch. The memory device stores first map data of the first storage device and second map data of the second storage device. The CXL switch is connected with the first storage device, the second storage device, and an external host through a first interface, and arbitrates communications between the first storage device, the second storage device, and the external host. The first storage device is connected with the memory device through a second interface. The second storage device is connected with the memory device through a third interface. The first interface, the second interface, and the third interface are physically separated from each other.

公开(公告)号：US11809363B1

公开(公告)日：2023-11-07

申请号：US17462753

申请日：2021-08-31

Applicant: Synopsys, Inc.

Inventor： Jishnu De ,  Jaspreet Singh Gambhir

IPC: G06F13/42 ,  G06F13/38 ,  G06F12/02 ,  G06F12/06 ,  G06F15/173

CPC classification number: G06F13/4221 ,  G06F12/0246 ,  G06F12/0646 ,  G06F13/387 ,  G06F15/17312

Abstract: A method for debugging an electronic subsystem is disclosed. The method includes converting a first message in a first protocol format received at a first functional logical block of a plurality of functional logical blocks of an electronic subsystem into a second message in a second protocol format at the first functional logical block, wherein the second message includes a unique identifier (UID), and generating a first trace file corresponding to the first functional logical block, wherein the first trace file includes the UID. The method includes forwarding the second message from the first functional logical block to a second functional logical block. The method includes generating a second trace file corresponding to the second functional logical block, wherein the second trace file includes the UID, and performing an analysis on the first and the second functional logical blocks.

公开(公告)号：US11809258B2

公开(公告)日：2023-11-07

申请号：US16820307

申请日：2020-03-16

Applicant: Apple Inc.

Inventor： Saurabh Garg ,  Karan Sanghi ,  Vladislav Petkov ,  Richard Solotke

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/3234 ,  G06F13/40 ,  G06F13/42 ,  G06F1/3203 ,  G06F1/3287 ,  G06F9/30 ,  G06F9/4401 ,  G06F1/24

CPC classification number: G06F1/325 ,  G06F1/3203 ,  G06F1/3253 ,  G06F1/3287 ,  G06F9/3004 ,  G06F9/4411 ,  G06F9/4418 ,  G06F13/404 ,  G06F13/4221 ,  G06F13/4273 ,  G06F13/4278 ,  G06F1/24 ,  Y02D10/00

Abstract: Methods and apparatus for isolation of sub-system resources (such as clocks, power, and reset) within independent domains. In one embodiment, each sub-system of a system has one or more dedicated power and clock domains that operate independent of other sub-system operation. For example, in an exemplary mobile device with cellular, WLAN and PAN connectivity, each such sub-system is connected to a common memory mapped bus function, yet can operate independently. The disclosed architecture advantageously both satisfies the power consumption limitations of mobile devices, and concurrently provides the benefits of memory mapped connectivity for high bandwidth applications on such mobile devices.

公开(公告)号：US20230352431A1

公开(公告)日：2023-11-02

申请号：US18300329

申请日：2023-04-13

Applicant: Intel Corporation

Inventor： MD Altaf Hossain ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy

IPC: H01L23/00 ,  G06F13/38 ,  H01L25/065 ,  G06F13/42 ,  G06F13/14

CPC classification number: H01L24/18 ,  G06F13/385 ,  H01L25/0655 ,  G06F13/4265 ,  G06F13/14 ,  G06F13/4221 ,  H01L25/0652

Abstract: An integrated circuit includes a package substrate that includes first and second electrical traces. The integrated circuit includes first, second, third, and fourth configurable dies, which are mounted on the package substrate. The first and second configurable dies are arranged in a first row. The third and fourth configurable dies are arranged in a second row, which is approximately parallel to the first row. The first and third configurable dies are arranged in a first column. The second and fourth configurable dies are arranged in a second column, which is approximately parallel to the first column. The first electrical trace couples the first and third configurable dies, and the second electrical trace couples the second and third configurable dies. The second electrical trace is oblique with respect to the first electrical trace. The oblique trace improves the latency of signals transmitted between dies and thereby increases the circuit operating speed.

公开(公告)号：US20230351231A1

公开(公告)日：2023-11-02

申请号：US18212170

申请日：2023-06-20

Applicant: QMware AG

Inventor： Georg Gesek

IPC: G06N10/00 ,  G06F7/57 ,  G06F13/42

CPC classification number: G06N10/00 ,  G06F7/57 ,  G06F13/4221 ,  G06F2213/0026

Abstract: Systems and methods involving quantum machines, hybrid quantum machines, aspects of quantum information technology and/or other features are disclosed. In one exemplary implementation, a system is provided comprising a quantum register that stores quantum information using qubits, wherein the qubits are configured to store the quantum information using particles or objects arranged in a lattice of quantum gates, a clock that provides a clock cycle to the quantum register, and a qubit-tie computing component coupled to the quantum register, wherein the qubit-tie computing component is configured to shift the quantum information between the qubits, wherein the system stores the qubits in different states using physical qualities, which may define qubits that are configured to be entangled and superposed at a same time. Further, the quantum register may comprise an entanglement component, and/or the qubit-tie computing component may comprise a superposition component.

公开(公告)号：US11804256B2

公开(公告)日：2023-10-31

申请号：US17870880

申请日：2022-07-22

Applicant: Kioxia Corporation

Inventor： Hajime Matsumoto

IPC: G11C5/14 ,  G11C11/4074 ,  G11C11/4076 ,  G06F13/42 ,  G11C5/06 ,  G06F13/40 ,  G11C11/4072

CPC classification number: G11C11/4074 ,  G06F13/409 ,  G06F13/4221 ,  G11C5/06 ,  G11C11/4072 ,  G11C11/4076

Abstract: According to one embodiment, a memory system is disclosed. The system includes a nonvolatile memory, a controller which controls the nonvolatile memory and to which a first voltage is supplied, and a circuit to which first and second signals from a host device are input, or the first signal is not input and the second signal is input from the host device, when the memory system is connected to the host device. The circuit converts a second voltage of the second signal into the first voltage when the first and second signal have the second voltage and the second voltage is lower than the first voltage, and does not convert a voltage of the second signal into the first voltage when the first signal is not input and the voltage of the second signal is the first voltage.

公开(公告)号：US11803503B2

公开(公告)日：2023-10-31

申请号：US17494821

申请日：2021-10-05

Applicant: MEDIATEK INC.

Inventor： Ching-Yi Wu

IPC: G06F13/42 ,  G06F13/40 ,  G06F1/3234 ,  G06F13/362

CPC classification number: G06F13/4221 ,  G06F1/3253 ,  G06F13/362 ,  G06F13/4004 ,  G06F2213/0026

Abstract: A chip includes a peripheral component interconnect express (PCIe) switch, a dual-mode device, and a signal transmission control circuit. The PCIe switch includes a first downstream port. The dual-mode device switches between a root complex (RC) mode and an endpoint (EP) mode. The signal transmission control circuit is coupled between the PCIe switch and the dual-mode device. The first downstream port communicates with the dual-mode device operating under the EP mode. The signal transmission control circuit allows an external PCIe device to communicate with the dual-mode device operating under the RC mode.

公开(公告)号：US20230342323A1

公开(公告)日：2023-10-26

申请号：US18345208

申请日：2023-06-30

Applicant: Mohannad Fahim Ali ,  Swadesh Choudhary ,  Joji Philip ,  David J. Harriman

Inventor： Mohannad Fahim Ali ,  Swadesh Choudhary ,  Joji Philip ,  David J. Harriman

IPC: G06F13/42

CPC classification number: G06F13/4221 ,  G06F2213/0026

Abstract: An interface for coupling an agent to a fabric supports a load/store interconnect protocol, where the I/O interconnect protocol includes a flit mode and a non-flit mode. A set of flit mode header formats are used when in the flit mode and a set of non-flit mode header formats are used when in the non-flit mode, the set of non-flit mode header formats including one or more non-flit mode fields. Interface logic determines that a link is trained to the non-flit mode and generates a header according to the set of flit mode header formats, where the header includes a field to indicate that a corresponding packet originated as a non-flit mode packet. One or more fields of the set of flit mode header formats are repurposed in the header to carry the one or more non-flit mode fields before sending the modified header over the interface.

公开(公告)号：US11792114B2

公开(公告)日：2023-10-17

申请号：US17594548

申请日：2020-03-23

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Duncan Roweth ,  Robert L. Alverson ,  Albert Cheng ,  Timothy J. Johnson

IPC: H04L12/26 ,  H04L45/28 ,  H04L45/028 ,  H04L45/125 ,  H04L45/00 ,  H04L45/122 ,  H04L47/76 ,  H04L49/15 ,  H04L49/00 ,  H04L69/40 ,  H04L47/10 ,  H04L49/9005 ,  H04L47/34 ,  H04L67/1097 ,  G06F13/16 ,  H04L45/021 ,  H04L47/12 ,  G06F13/42 ,  H04L47/2441 ,  H04L47/30 ,  H04L47/62 ,  H04L47/24 ,  H04L49/90 ,  G06F13/38 ,  G06F13/40 ,  H04L45/745 ,  H04L47/2483 ,  H04L47/629 ,  H04L47/80 ,  H04L49/101 ,  H04L45/12 ,  H04L47/122 ,  G06F12/1036 ,  G06F15/173 ,  H04L43/10 ,  H04L45/42 ,  H04L47/11 ,  G06F12/0862 ,  G06F12/1045 ,  H04L47/32 ,  G06F9/54 ,  G06F13/14 ,  G06F9/50 ,  H04L47/22 ,  H04L47/52 ,  H04L47/6275 ,  H04L45/24 ,  H04L45/7453 ,  H04L45/16 ,  H04L69/22 ,  H04L47/762 ,  H04L47/78 ,  H04L47/20 ,  H04L49/9047 ,  H04L1/00 ,  H04L43/0876 ,  H04L47/2466 ,  H04L47/625 ,  H04L69/28

CPC classification number: H04L45/28 ,  G06F9/505 ,  G06F9/546 ,  G06F12/0862 ,  G06F12/1036 ,  G06F12/1063 ,  G06F13/14 ,  G06F13/16 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F15/17331 ,  H04L1/0083 ,  H04L43/0876 ,  H04L43/10 ,  H04L45/021 ,  H04L45/028 ,  H04L45/122 ,  H04L45/123 ,  H04L45/125 ,  H04L45/16 ,  H04L45/20 ,  H04L45/22 ,  H04L45/24 ,  H04L45/38 ,  H04L45/42 ,  H04L45/46 ,  H04L45/566 ,  H04L45/70 ,  H04L45/745 ,  H04L45/7453 ,  H04L47/11 ,  H04L47/12 ,  H04L47/122 ,  H04L47/18 ,  H04L47/20 ,  H04L47/22 ,  H04L47/24 ,  H04L47/2441 ,  H04L47/2466 ,  H04L47/2483 ,  H04L47/30 ,  H04L47/32 ,  H04L47/323 ,  H04L47/34 ,  H04L47/39 ,  H04L47/52 ,  H04L47/621 ,  H04L47/626 ,  H04L47/629 ,  H04L47/6235 ,  H04L47/6275 ,  H04L47/76 ,  H04L47/762 ,  H04L47/781 ,  H04L47/80 ,  H04L49/101 ,  H04L49/15 ,  H04L49/30 ,  H04L49/3009 ,  H04L49/3018 ,  H04L49/3027 ,  H04L49/90 ,  H04L49/9005 ,  H04L49/9021 ,  H04L49/9036 ,  H04L49/9047 ,  H04L67/1097 ,  H04L69/22 ,  H04L69/40 ,  G06F2212/50 ,  G06F2213/0026 ,  G06F2213/3808 ,  H04L69/28

Abstract: A network interface controller (NIC) capable of efficient management of non-idempotent operations is provided. The NIC can be equipped with a network interface, storage management logic block, and an operation management logic block. During operation, the network interface can receive a request for an operation from a remote device. The storage management logic block can store, in a local data structure, outcome of operations executed by the NIC. The operation management logic block can determine whether the NIC has previously executed the operation. If the NIC has previously executed the operation, the operation management logic block can obtain an outcome of the operation from the data structure and generate a response comprising the obtained outcome for responding to the request.