公开(公告)号：US20180315864A1

公开(公告)日：2018-11-01

申请号：US15583289

申请日：2017-05-01

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Fabio Alessio MARINO ,  Qingqing LIANG ,  Francesco CAROBOLANTE ,  Seung Hyuk KANG

IPC: H01L29/93 ,  H01L29/66

CPC classification number: H01L29/93 ,  H01L29/0649 ,  H01L29/36 ,  H01L29/66174 ,  H01L29/94

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor variable capacitor, and techniques for fabricating the same, implemented using a threshold voltage implant region. For example, the semiconductor variable capacitor generally includes a first non-insulative region disposed above a first semiconductor region, a second non-insulative region disposed above the first semiconductor region, and a threshold voltage (Vt) implant region interposed between the first non-insulative region and the first semiconductor region and disposed adjacent to the second non-insulative region. In certain aspects, the semiconductor variable capacitor also includes a control region disposed above the first semiconductor region such that a capacitance between the first non-insulative region and the second non-insulative region is configured to be adjusted by varying a control voltage applied to the control region.

公开(公告)号：US20180240898A1

公开(公告)日：2018-08-23

申请号：US15614471

申请日：2017-06-05

Applicant: QUALCOMM Incorporated

Inventor： Gengming TAO ,  Bin YANG ,  Xia LI ,  Miguel MIRANDA CORBALAN

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7371 ,  H01L29/0696 ,  H01L29/0813 ,  H01L29/0817 ,  H01L29/1004 ,  H01L29/42304 ,  H01L29/66242

Abstract: A heterojunction bipolar transistor unit cell may include a compound semiconductor substrate. The heterojunction bipolar transistor unity may also include a base mesa on the compound semiconductor substrate. The base mesa may include a collector region on the compound semiconductor substrate and a base region on the collector region. The heterojunction bipolar transistor unity may further include a single emitter mesa on the base mesa.

公开(公告)号：US20160268002A1

公开(公告)日：2016-09-15

申请号：US14656699

申请日：2015-03-12

Applicant: QUALCOMM Incorporated

Inventor： Xiaonan CHEN ,  Zhongze WANG ,  Xia LI

IPC: G11C17/08

CPC classification number: G11C17/08 ,  G11C7/04 ,  G11C17/12 ,  G11C17/123

Abstract: An OTP memory array includes a plurality of differential P-channel metal oxide semiconductor (PMOS) OTP memory cells programmable and readable in predetermined states of program and read operations, and is capable of providing sufficient margins against global process variations and temperature variations while being compatible with standard logic fin-shaped field effect transistor (FinFET) processes to obviate the need for additional masks and costs associated with additional masks.

Abstract translation: OTP存储器阵列包括在预定的程序和读取操作状态下可编程和可读的多个差分P沟道金属氧化物半导体（PMOS）OTP存储器单元，并且能够在兼容的同时为全局工艺变化和温度变化提供足够的余量 具有标准逻辑鳍状场效应晶体管（FinFET）处理，以避免需要额外的掩模和与附加掩模相关联的成本。

公开(公告)号：US20160155748A1

公开(公告)日：2016-06-02

申请号：US14556983

申请日：2014-12-01

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Jeffrey Junhao XU ,  Zhongze WANG ,  Bin YANG ,  Xiaonan CHEN ,  Yu LU

IPC: H01L27/115 ,  H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L21/02 ,  H01L29/788 ,  H01L29/51

CPC classification number: H01L21/28088 ,  G11C16/0408 ,  H01L21/02148 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/28273 ,  H01L21/28291 ,  H01L29/4966 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7851 ,  H01L29/7883

Abstract: Non-volatile memory devices and logic devices are fabricated using processes compatible with high dielectric constant/metal gate (HK/MG) processes for increased cell density and larger scale integration. A doped oxide layer, such as a silicon-doped hafnium oxide (HfO2) layer, is implemented as a ferroelectric dipole layer in a non-volatile memory device

Abstract translation: 使用与高介电常数/金属栅（HK / MG）工艺兼容的工艺制造非易失性存储器件和逻辑器件，用于增加电池密度和更大规模的集成。 掺杂氧化物层，例如掺杂硅的氧化铪（HfO 2）层，被实现为非易失性存储器件中的铁电偶极子层

公开(公告)号：US20160093672A1

公开(公告)日：2016-03-31

申请号：US14499004

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Daniel Wayne PERRY, JR. ,  Seung Hyuk KANG

IPC: H01L27/24 ,  G11C13/00 ,  H01L45/00

CPC classification number: H01L27/2418 ,  G11C13/0007 ,  G11C13/0069 ,  G11C17/165 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/16

Abstract: Methods and apparatuses, wherein the method includes providing a logic device. The method substantially surrounds a metal gate with a transition metal oxide on at least one side, wherein the transition metal oxide is comprised of hafnium oxalate and silicon dioxide. The method provides a bottom electrode (BE), wherein the BE is comprised of at least one of silicon or tungsten.

Abstract translation: 方法和装置，其中所述方法包括提供逻辑装置。 该方法基本上围绕在至少一侧上具有过渡金属氧化物的金属栅极，其中过渡金属氧化物由草酸铪和二氧化硅组成。 该方法提供底电极（BE），其中BE由硅或钨中的至少一种构成。

公开(公告)号：US20160043304A1

公开(公告)日：2016-02-11

申请号：US14454509

申请日：2014-08-07

Applicant: QUALCOMM Incorporated

Inventor： Wei-Chuan CHEN ,  Xiaochun ZHU ,  Xia LI ,  Yu LU ,  Chando PARK ,  Seung Hyuk KANG

IPC: H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L43/02

CPC classification number: H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: A perpendicular magnetic tunnel junction (pMTJ) device includes a perpendicular reference layer, a tunnel barrier layer on a surface of the perpendicular reference layer, and a perpendicular free layer on a surface of the tunnel barrier layer. The pMTJ device also includes a dielectric passivation layer on the tunnel barrier layer and surrounding the perpendicular free layer. The pMTJ device further includes a high permeability material on the dielectric passivation layer that is configured to be magnetized by the perpendicular reference layer and to provide a stray field to the perpendicular free layer that compensates for a stray field from the perpendicular reference layer.

Abstract translation: 垂直磁隧道结（pMTJ）器件包括垂直参考层，垂直参考层表面上的隧道势垒层和隧道势垒层表面上的垂直自由层。 pMTJ器件还包括在隧道势垒层上的电介质钝化层并围绕垂直自由层。 pMTJ器件还包括介电钝化层上的高磁导率材料，其被配置为由垂直参考层磁化，并且向垂直自由层提供杂散场，该杂散场补偿来自垂直参考层的杂散场。

公开(公告)号：US20240321965A1

公开(公告)日：2024-09-26

申请号：US18189442

申请日：2023-03-24

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Xia LI ,  Chih-Sung YANG ,  Kwanyong LIM ,  Ming-Huei LIN ,  Hyunwoo PARK ,  Haining YANG

IPC: H01L29/08 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L21/76841 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/088 ,  H01L29/6656

Abstract: Disclosed are devices that include a contact for electrical connection with a source/drain. The contact occupies a full width of a contact well other than areas occupied by sidewall spacers. As a result, high resistivity (due to the presence of liners and nucleation layers within the contact well in conventional devices) is reduced or eliminated.

公开(公告)号：US20240321631A1

公开(公告)日：2024-09-26

申请号：US18190024

申请日：2023-03-24

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Junjing BAO ,  Bin YANG ,  Biswa Ranjan PANDA ,  Ramesh MANCHANA

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53257 ,  H01L23/5329

Abstract: An integrated circuit (IC) includes back-end-of-line (BEOL) interconnects in a first intermetal dielectric (IMD) layer on a substrate. The IC also includes second BEOL interconnects on the first IMD layer, coupled to the first BEOL interconnects through first BEOL vias in the first IMD layer. The IC further includes a second IMD layer on the second BEOL interconnects to seal airgaps between the plurality of second BEOL interconnects. The IC also includes etch stop spacers on portions of sidewalls of the second BEOL interconnects to separate the portions of the sidewalls from the second IMD layer. The IC further includes third BEOL interconnects on the second IMD layer and coupled to one or more of the second BEOL interconnects through second BEOL vias in the second IMD layer.

公开(公告)号：US20240204109A1

公开(公告)日：2024-06-20

申请号：US18068992

申请日：2022-12-20

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Junjing BAO ,  Giridhar NALLAPATI

IPC: H01L29/786 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/78696 ,  H01L21/823807 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/0673

Abstract: Disclosed are complementary field effect transistors (CFETs) with balanced n and p drive current, and methods for making the same. In an aspect, a CFET structure comprises an nFET with horizontal p-doped nanosheet channels arranged in a first vertical stack, each horizontal p-doped nanosheet channel having a width W1, and connecting a first source contact to a first drain contact through a first gate-all-around (GAA) region having a length L1. The CFET structure further comprises a pFET with horizontal n-doped nanosheet channels arranged in a second vertical stack disposed on the first vertical stack, each horizontal n-doped nanosheet channel having a width W2, and connecting a second source contact to a second drain contact through a second GAA region having a length L2, wherein W2/L2 is not equal to W1/L1.

公开(公告)号：US20230058318A1

公开(公告)日：2023-02-23

申请号：US17404919

申请日：2021-08-17

Applicant: QUALCOMM Incorporated

Inventor： Udayakiran Kumar YALLAMARAJU ,  Xia LI ,  Pankaj DESHMUKH ,  Vajram GHANTASALA ,  Bin YANG ,  Vishal MISHRA ,  Bharatheesha Sudarshan JAGIRDAR ,  Arun Sundaresan IYER ,  Amod PHADKE ,  Vanamali BHAT

IPC: H03K5/156 ,  H03K5/134

Abstract: A system includes a first park circuit having a signal input, an output, and a control input. The system also includes a first signal path having an input and an output, wherein the input of the first signal path is coupled to the output of the first park circuit. The system also includes a second park circuit having a signal input, an output, and a control input, wherein the signal input of the second park circuit is coupled to the output of the first signal path. The system further includes a second signal path having an input and an output, wherein the input of the second signal path is coupled to the output of the second park circuit.