公开(公告)号：US20250133772A1

公开(公告)日：2025-04-24

申请号：US18493634

申请日：2023-10-24

Applicant: QUALCOMM Incorporated

Inventor： Kwanyong LIM ,  Hyunwoo PARK ,  Junjing BAO ,  Chih-Sung YANG ,  Ming-Huei LIN ,  Haining YANG

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A gate all around (GAA) field effect transistor (GAA FET) is described. The GAA FET includes a substrate, having a nanosheet structure on the substrate. The GAA FET also includes a source/drain (SD) region in the substrate and coupled to a first end of the nanosheet structure. The GAA FET further includes a drain/source (DS) region in the substrate and coupled to a second end opposite the first end of the nanosheet structure. The GAA FET also includes a metal gate on the nanosheet structure to define channels between the source/drain region and the drain/source region. The GAA FET further includes a trench oxide blocking a bottom channel of the channels.

公开(公告)号：US20250072105A1

公开(公告)日：2025-02-27

申请号：US18455511

申请日：2023-08-24

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Junjing BAO ,  Biswa Ranjan PANDA ,  Ramesh MANCHANA

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775

Abstract: An integrated circuit (IC) device includes an N-type field effect transistor (FET). The N-type FET includes an N-type vertical structure on a substrate, including an N-type gate region having a first normal-k oxide layer on a semiconductor layer of the N-type vertical structure, an N-type work-function metal (WFM) layer on the first normal-k oxide layer and sidewall spacers of the N-type gate region, and a first metal gate on the N-type WFM layer. The IC device includes a first P-type FET. The first P-type FET includes a first P-type vertical structure on the substrate, including a first P-type gate region having a second normal-k oxide layer on a first semiconductor layer of the first P-type vertical structure, a first P-type WFM layer on the second normal-k oxide layer and sidewall spacers of the first P-type gate region, and a second metal gate on the first P-type WFM layer.

公开(公告)号：US20250046716A1

公开(公告)日：2025-02-06

申请号：US18365791

申请日：2023-08-04

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  John Jianhong ZHU ,  Giridhar NALLAPATI

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: A via with a modified reverse selective barrier structure and method for making the same are disclosed. In an aspect, a via structure comprises a first metal structure providing an electrical conductor (e.g., copper) oriented vertically; a second structure (e.g., cobalt) surrounding and in contact with a bottom and sides of the first metal structure; a third structure (e.g., metallic tantalum) surrounding and in contact with a bottom and sides of the second structure; a fourth structure (e.g., ruthenium) disposed beneath and in contact with a bottom of the third structure; and a fifth structure (e.g., amorphous tantalum nitride) surrounding and in contact with sides of the third structure; wherein a bottom surface of the fourth structure is in contact with a top surface of a metallization layer. In some aspects, the fifth structure is also surrounding and in contact with sides of the fourth structure.

公开(公告)号：US20210233909A1

公开(公告)日：2021-07-29

申请号：US16751371

申请日：2020-01-24

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Ye LU ,  Peijie FENG ,  Chenjie TANG ,  Xiaochun ZHU

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8238 ,  H01L29/66

Abstract: Certain aspects of the present disclosure relate to a gate-all-around (GAA) semiconductor device. One example GAA semiconductor device includes a plurality of nanosheet stack structures disposed vertically above a horizontal plane of a substrate, wherein: each nanosheet stack structure of the plurality of nanosheet stack structures comprises one or more nanosheets; the one or more nanosheets of a first nanosheet stack structure of the plurality of nanosheet stack structures comprise a first semiconductor material; and the one or more nanosheets of a second nanosheet stack structure of the plurality of nanosheet stack structures comprise a second semiconductor material different from the first semiconductor material.

公开(公告)号：US20190221645A1

公开(公告)日：2019-07-18

申请号：US16288558

申请日：2019-02-28

Applicant: QUALCOMM Incorporated

Inventor： Ye LU ,  Junjing BAO ,  Bin YANG ,  Lixin GE ,  Yun YUE

IPC: H01L29/16 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/72 ,  H01L29/10

CPC classification number: H01L29/1606 ,  H01L21/02115 ,  H01L21/02181 ,  H01L21/02271 ,  H01L29/1004 ,  H01L29/1608 ,  H01L29/66037 ,  H01L29/66068 ,  H01L29/6656 ,  H01L29/72 ,  H01L29/785

Abstract: An integrated circuit (IC) device may include a semiconductor structure. The semiconductor structure may include a source contact, a drain contact, and a gate. A first fluorocarbon spacer may be between the gate and the source contact. A second fluorocarbon spacer may be between the gate and the drain contact.

公开(公告)号：US20160351677A1

公开(公告)日：2016-12-01

申请号：US14723199

申请日：2015-05-27

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Haining YANG ,  Yanxiang LIU ,  Jeffrey Junhao XU

IPC: H01L29/49 ,  H01L21/02 ,  H01L21/311 ,  H01L29/40 ,  H01L27/088 ,  H01L21/3105 ,  H01L21/3213 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/288

CPC classification number: H01L29/495 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/288 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/32134 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: A sacrificial cap is grown on an upper surface of a conductor. A dielectric spacer is against a side of the conductor. An upper dielectric side spacer is formed on a sidewall of the sacrificial cap. The sacrificial cap is selectively etched, leaving a cap recess, and the upper dielectric side spacer facing the cap recess. Silicon nitride is filled in the cap recess, to form a center cap and a protective cap having center cap and the upper dielectric spacer.

Abstract translation: 在导体的上表面上生长牺牲帽。 电介质隔离物抵靠导体的一侧。 在绝缘帽的侧壁上形成上绝缘侧绝缘体。 选择性地蚀刻牺牲帽，留下盖子凹槽，并且上电介质侧隔片面向盖凹槽。 氮化硅填充在盖凹部中，以形成中心帽和具有中心盖和上部电介质间隔物的保护帽。

公开(公告)号：US20240379770A1

公开(公告)日：2024-11-14

申请号：US18316862

申请日：2023-05-12

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Junjing BAO ,  John Jianhong ZHU

IPC: H01L29/40 ,  H01L21/311 ,  H01L27/088 ,  H01L29/417

Abstract: A self-aligned contact (SAC) and method for making the same is disclosed. In an aspect a field effect transistor (FET) structure comprises a channel connecting a first source or drain (S/D) region to a second S/D region, a gate structure, comprising a multi-layer metal gate between gate spacers, disposed above a gate region that at least partially surrounds the channel, a self-alignment structure, also referred to as a “hat”, disposed above the gate structure and covering at least the multi-layer metal gate and the gate spacers, and a first S/D contact that is self-aligned to the hat and connected to the first S/D region. During fabrication, a self-assembly monolayer (SAM) is used to precisely align the hat over the multi-layer metal gate. The S/D contacts are then self-aligned to the hat, even if the etch mask has an overlay error. The hat also shields the gate structure during an etch.

公开(公告)号：US20240243131A1

公开(公告)日：2024-07-18

申请号：US18098633

申请日：2023-01-18

Applicant: QUALCOMM Incorporated

Inventor： Ming-Huei LIN ,  Haining YANG ,  Junjing BAO

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/31155

Abstract: A fin field effect transistor (FinFET) is described. The FinFET includes a substrate and a shallow trench isolation (STI) region on the substrate. The FinFET also includes a first fin structure on the substrate and extending through the STI region. The FinFET further includes a second fin structure on the substrate and extending through the STI region. The FinFET also includes a metal gate on the STI region, on the first fin structure, and on the second fin structure. The metal gate is composed of a first sub-metal gate cut line filled with a first stressor material, and a second sub-metal gate cut line filled with a second stressor material different from the first stressor material.

公开(公告)号：US20220336607A1

公开(公告)日：2022-10-20

申请号：US17235491

申请日：2021-04-20

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  John Jianhong ZHU ,  Giridhar NALLAPATI

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/417 ,  H01L27/088

Abstract: Disclosed are apparatuses including a transistor cell and methods of fabricating the transistor cell. The transistor cell may include a substrate, an active region and a gate having a gate contact in the active region. The transistor cell may further include a first portion of a spacer of the gate contact formed from a first material, and a second portion of the spacer of the gate contact formed from a second material.

公开(公告)号：US20220262723A1

公开(公告)日：2022-08-18

申请号：US17176969

申请日：2021-02-16

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  John Jianhong ZHU ,  Haining YANG

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

Abstract: An integrated circuit (IC) having an interconnect structure with metal lines with different conductive materials for different widths and a method for fabricating such an IC. An example IC generally includes an active layer and an interconnect structure disposed thereabove and comprising a plurality of metal layers and one or more vias landing on metal lines. At least one of the plurality of metal layers comprises one or more first metal lines and one or more second metal lines. The one or more first metal lines have one or more first widths and comprise a first conductive material including copper. The one or more second metal lines have one or more second widths and comprise a second conductive material different from the first conductive material, where the second widths are narrower than the first widths. The vias have one or more third widths and comprise a third conductive material.