公开(公告)号：US20170040324A1

公开(公告)日：2017-02-09

申请号：US14817441

申请日：2015-08-04

Applicant: QUALCOMM Incorporated

Inventor： Haining YANG ,  Yanxiang LIU

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L27/088 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/02164 ,  H01L21/26513 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823892 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7845

Abstract: A finFET device according to some examples herein may include an active gate element above an active fin element and a dummy fin element that partially breaks the active gate element. In another example, a dummy gate element adjacent to an active gate element contains a dummy fin element that partially breaks the dummy gate element. In another example, a first dummy fin element partially breaks an active gate element and a second dummy fin element partially breaks a dummy gate element. In another example, the dummy fin element is of the same material as the active fin element. In another example, the dummy fin element partially breaks a gate element but does not extend to the substrate like the active fin element.

Abstract translation: 根据这里的一些示例的finFET器件可以包括有源鳍元件上方的有源栅极元件和部分地断开有源栅极元件的虚设鳍元件。 在另一示例中，与有源栅极元件相邻的伪栅极元件包含部分地断开伪栅极元件的虚设鳍元件。 在另一个示例中，第一虚拟翅片元件部分地中断有源栅极元件，并且第二虚设鳍元件部分地断开伪栅极元件。 在另一个示例中，虚拟翅片元件具有与活动翅片元件相同的材料。 在另一个示例中，虚拟鳍片元件部分地打破栅极元件，但是不像活性鳍片元件那样延伸到衬底。

公开(公告)号：US20170236815A1

公开(公告)日：2017-08-17

申请号：US15582770

申请日：2017-05-01

Applicant: QUALCOMM Incorporated

Inventor： Yanxiang LIU ,  Haining YANG

IPC: H01L27/02 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0207 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7851

Abstract: The n-type to p-type fin-FET strength ratio in an integrated logic circuit may be tuned by the use of cut regions in the active and dummy gate electrodes. In some examples, separate cut regions for the dummy gate electrodes and the active gate electrode may be used to allow for different lengths of gate pass-active regions resulting in appropriately tuned integrated logic circuits.

公开(公告)号：US20180197743A1

公开(公告)日：2018-07-12

申请号：US15910929

申请日：2018-03-02

Applicant: QUALCOMM Incorporated

Inventor： Da YANG ,  Yanxiang LIU ,  Jun YUAN ,  Kern RIM

IPC: H01L21/28 ,  H01L29/66 ,  H01L21/3213 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/28123 ,  H01L29/66795 ,  H01L29/7851

Abstract: Multigate devices and fabrication methods that mitigate the layout effects are described. In conventional processes to fabricate multigate semiconductor devices such as FinFET devices, long isolation cut masks may be used. This can lead to undesirable layout effects. To mitigate or eliminate the layout effect, fabrication methods are proposed in which the interlayer dielectric (ILD) layer remains intact at the gate cut location during the fabrication process.

公开(公告)号：US20180076139A1

公开(公告)日：2018-03-15

申请号：US15352342

申请日：2016-11-15

Applicant: QUALCOMM Incorporated

Inventor： Yanxiang LIU ,  Haining YANG ,  Youseok SUH ,  Jihong CHOI ,  Junjing BAO

IPC: H01L23/535 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266

Abstract: A semiconductor device may include a source/drain contact trench adjacent to a gate. The source/drain contact trench may include a first portion and a second portion on the first portion. The semiconductor device also may include an insulating contact spacer liner within the source/drain contact trench. The insulating contact spacer liner contacts the first portion but not the second portion of the source/drain contact trench. The semiconductor device may further include a conductive material within the insulating contact spacer liner and the second portion of the source/drain contact trench. The conductive material may land in a source/drain region of the semiconductor device.

公开(公告)号：US20160284836A1

公开(公告)日：2016-09-29

申请号：US14668476

申请日：2015-03-25

Applicant: QUALCOMM Incorporated

Inventor： Yanxiang LIU ,  Haining YANG

IPC: H01L29/78 ,  H01L29/423

CPC classification number: H01L27/0207 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7851

Abstract: The n-type to p-type fin-FET strength ratio in an integrated logic circuit may be tuned by the use of cut regions in the active and dummy gate electrodes. In some examples, separate cut regions for the dummy gate electrodes and the active gate electrode may be used to allow for different lengths of gate pass-active regions resulting in appropriately tuned integrated logic circuits.

Abstract translation: 集成逻辑电路中的n型至p型鳍FET强度比可以通过在有源和虚拟栅电极中使用切割区来调节。 在一些示例中，虚拟栅电极和有源栅电极的单独切割区域可以用于允许不同长度的栅极通过有源区域，从而导致适当调谐的集成逻辑电路。

公开(公告)号：US20160351677A1

公开(公告)日：2016-12-01

申请号：US14723199

申请日：2015-05-27

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Haining YANG ,  Yanxiang LIU ,  Jeffrey Junhao XU

IPC: H01L29/49 ,  H01L21/02 ,  H01L21/311 ,  H01L29/40 ,  H01L27/088 ,  H01L21/3105 ,  H01L21/3213 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/288

CPC classification number: H01L29/495 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/288 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/32134 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: A sacrificial cap is grown on an upper surface of a conductor. A dielectric spacer is against a side of the conductor. An upper dielectric side spacer is formed on a sidewall of the sacrificial cap. The sacrificial cap is selectively etched, leaving a cap recess, and the upper dielectric side spacer facing the cap recess. Silicon nitride is filled in the cap recess, to form a center cap and a protective cap having center cap and the upper dielectric spacer.

Abstract translation: 在导体的上表面上生长牺牲帽。 电介质隔离物抵靠导体的一侧。 在绝缘帽的侧壁上形成上绝缘侧绝缘体。 选择性地蚀刻牺牲帽，留下盖子凹槽，并且上电介质侧隔片面向盖凹槽。 氮化硅填充在盖凹部中，以形成中心帽和具有中心盖和上部电介质间隔物的保护帽。

公开(公告)号：US20180219009A1

公开(公告)日：2018-08-02

申请号：US15418651

申请日：2017-01-27

Applicant: QUALCOMM Incorporated

Inventor： Yanxiang LIU ,  Haining YANG

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/308 ,  H01L21/306 ,  H01L21/762 ,  H01L21/3115 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/31155 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/785

Abstract: To avoid the problems associated with low density spin on dielectrics, some examples of the disclosure include a finFET with an oxide material having different densities. For example, one such finFET may include an oxide material located in a gap between adjacent fins, the oxide material directly contacts the adjacent fins of the plurality of fins with a first density proximate to a top layer of the oxide material and a second density proximate to a bottom layer of the oxide material and wherein the first density is greater than the second density.

公开(公告)号：US20180082846A1

公开(公告)日：2018-03-22

申请号：US15271867

申请日：2016-09-21

Applicant: QUALCOMM Incorporated

Inventor： Da YANG ,  Yanxiang LIU ,  Jun YUAN ,  Kern RIM

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/3213

CPC classification number: H01L21/28123 ,  H01L21/32139 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: Multigate devices and fabrication methods that mitigate the layout effects are described. In conventional processes to fabricate multigate semiconductor devices such as FinFET devices, long isolation cut masks may be used. This can lead to undesirable layout effects. To mitigate or eliminate the layout effect, fabrication methods are proposed in which the interlayer dielectric (ILD) layer remains intact at the gate cut location during the fabrication process.

公开(公告)号：US20160300948A1

公开(公告)日：2016-10-13

申请号：US14680711

申请日：2015-04-07

Applicant: QUALCOMM Incorporated

Inventor： Haining YANG ,  Yanxiang LIU

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/10 ,  H01L27/088 ,  H01L29/423

CPC classification number: H01L29/7845 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/1037 ,  H01L29/4232 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7856

Abstract: A semiconductor fin includes a channel region. A gate-stressor member, formed of a metal, extends transverse to the fin and includes gate surfaces that straddle the fin in the channel region. The gate-stressor member has a configuration that includes a partial cut spaced from the fin by a cut distance. The configuration causes, through the gate surfaces, a transverse stress in the fin, having a magnitude that corresponds to the cut distance. Transverse stressor members, formed of a metal, straddle the fin at regions outside of the channel region and cause, at the regions outside of the channel region, additional transverse stresses in the fin. The magnitude that corresponds to the cut distance, in combination with the additional transverse stresses, induces a longitudinal compressive strain in the channel region.

Abstract translation: 半导体鳍片包括沟道区域。 由金属形成的闸应力部件横向于翅片延伸并且包括在通道区域中跨过翅片的门表面。 闸门应力器构件具有包括与翅片间隔开切割距离的部分切割的构造。 该结构通过栅极表面导致鳍中的横向应力，其具有对应于切割距离的大小。 由金属形成的横向应力器构件在通道区域外的区域跨越翅片，并且在通道区域外的区域处引起翅片中额外的横向应力。 对应于切割距离的大小与附加的横向应力相结合，在通道区域中引起纵向压缩应变。