公开(公告)号：US20210313326A1

公开(公告)日：2021-10-07

申请号：US16840964

申请日：2020-04-06

Applicant: QUALCOMM Incorporated

Inventor： Kwanyong LIM ,  Ye LU ,  Lixin GE

IPC: H01L27/092 ,  H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: Certain aspects of the present disclosure generally relate to transistors in a layered arrangement. An example semiconductor device generally includes a substrate, an n-type metal-oxide-semiconductor (NMOS) transistor, and a p-type metal-oxide-semiconductor (PMOS) transistor. The NMOS transistor is disposed above the substrate and is a gate-all-around (GAA) field-effect transistor (FET). The PMOS transistor is disposed above the substrate, is a fin field-effect transistor (finFET), and is in a layered arrangement with the NMOS transistor.

公开(公告)号：US20190103320A1

公开(公告)日：2019-04-04

申请号：US15723224

申请日：2017-10-03

Applicant: QUALCOMM Incorporated

Inventor： Lixin GE ,  Bin YANG ,  Ye LU ,  Junjing BAO ,  Periannan CHIDAMBARAM

IPC: H01L21/8234 ,  H01L27/06 ,  H01L23/522

Abstract: Middle-of-line (MOL) shielded gate in integrated circuits (ICs) are disclosed. One or more metal resistors are fabricated in a MOL layer in the IC to reduce gate to drain parasitic capacitance in the semiconductor area. By fabricating a metal resistor in the MOL layer, the metal resistor can be localized close to semiconductor devices to more effectively reduce parasitic capacitance of the semiconductor devices without adding costs or defects to the current fabrication processes. The current fabrication processes may be used to create contacts in the MOL to fabricate the metal resistor.

公开(公告)号：US20180342585A1

公开(公告)日：2018-11-29

申请号：US15672017

申请日：2017-08-08

Applicant: QUALCOMM Incorporated

Inventor： Ye LU ,  Junjing BAO ,  Bin YANG ,  Lixin GE ,  Yun YUE

IPC: H01L29/16 ,  H01L21/02 ,  H01L29/66 ,  H01L29/10 ,  H01L29/72

CPC classification number: H01L29/1606 ,  H01L21/02115 ,  H01L21/02181 ,  H01L21/02271 ,  H01L29/1004 ,  H01L29/1608 ,  H01L29/66037 ,  H01L29/66068 ,  H01L29/6656 ,  H01L29/72 ,  H01L29/785

Abstract: An integrated circuit (IC) device may include a semiconductor structure. The semiconductor structure may include a source contact, a drain contact, and a gate. A first fluorocarbon spacer may be between the gate and the source contact. A second fluorocarbon spacer may be between the gate and the drain contact.

公开(公告)号：US20210005604A1

公开(公告)日：2021-01-07

申请号：US16918770

申请日：2020-07-01

Applicant: Qualcomm Incorporated

Inventor： Lixin GE ,  Ye LU ,  John Jianhong ZHU

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/775 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/033 ,  H01L29/66

Abstract: Methods and apparatuses for different types of non-planar transistors within a stack are presented. The apparatus includes a p-type transistor and an n-type transistor arranged in a stack vertically above a substrate, the p-type transistor and the n-type transistor being non-planar transistors. The p-type transistor includes a p-type channel and a first set of work function layer. The first set of work function layer surrounds the p-type channel. The p-type channel is configured for p-type conductivity based on the first set of work function layer. The n-type transistor includes an n-type channel and a second set of work function layer. The second set of work function layer surrounds the n-type channel. The n-type channel is configured for n-type conductivity based on the second set of work function layer. The first set of work function layer and the second set of work function layer are different.

公开(公告)号：US20190221645A1

公开(公告)日：2019-07-18

申请号：US16288558

申请日：2019-02-28

Applicant: QUALCOMM Incorporated

Inventor： Ye LU ,  Junjing BAO ,  Bin YANG ,  Lixin GE ,  Yun YUE

IPC: H01L29/16 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/72 ,  H01L29/10

CPC classification number: H01L29/1606 ,  H01L21/02115 ,  H01L21/02181 ,  H01L21/02271 ,  H01L29/1004 ,  H01L29/1608 ,  H01L29/66037 ,  H01L29/66068 ,  H01L29/6656 ,  H01L29/72 ,  H01L29/785

Abstract: An integrated circuit (IC) device may include a semiconductor structure. The semiconductor structure may include a source contact, a drain contact, and a gate. A first fluorocarbon spacer may be between the gate and the source contact. A second fluorocarbon spacer may be between the gate and the drain contact.

公开(公告)号：US20210320059A1

公开(公告)日：2021-10-14

申请号：US16846591

申请日：2020-04-13

Applicant: QUALCOMM Incorporated

Inventor： Ye LU ,  John Jianhong ZHU ,  Lixin GE

IPC: H01L23/522 ,  H01L49/02 ,  H01L23/528

Abstract: Certain aspects of the present disclosure generally relate to a hybrid back-end-of-line (BEOL) dielectric for a high capacitance density metal-oxide-metal (MOM) capacitor, especially in lower BEOL layers. One example semiconductor device includes an active layer and a first metal layer disposed above the active layer. The first metal layer generally includes: a first electrode; a second electrode, wherein the first and second electrodes have interdigitated fingers; a first dielectric material disposed at least partially between at least two adjacent fingers of the first and second electrodes; and a second dielectric material, wherein the second dielectric material is different from the first dielectric material and wherein the first electrode, the second electrode, and the first dielectric material compose a portion of a metal-oxide-metal (MOM) capacitor.

公开(公告)号：US20150028452A1

公开(公告)日：2015-01-29

申请号：US14512191

申请日：2014-10-10

Applicant: QUALCOMM INCORPORATED

Inventor： John J. ZHU ,  Bin YANG ,  PR CHIDAMBARAM ,  Lixin GE ,  Jihong CHOI

IPC: H01L23/522 ,  H01L49/02

CPC classification number: H01L23/538 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A complementary back end of line (BEOL) capacitor (CBC) structure includes a metal oxide metal (MOM) capacitor structure. The MOM capacitor structure is coupled to a first upper interconnect layer of an interconnect stack of an integrated circuit (IC) device. The MOM capacitor structure includes a lower interconnect layer of the interconnect stack. The CBC structure also includes a second upper interconnect layer of the interconnect stack coupled to the MOM capacitor structure. The CBC structure also includes a metal insulator metal (MIM) capacitor layer between the first upper interconnect layer and the second upper interconnect layer. In addition, CBC structure also includes a MIM capacitor structure coupled to the MOM capacitor structure. The MIM capacitor structure includes a first capacitor plate having a portion of the first upper interconnect layer, and a second capacitor plate having a portion of the MIM capacitor layer(s).

Abstract translation: 互补的后端（BEOL）电容器（CBC）结构包括金属氧化物金属（MOM）电容器结构。 MOM电容器结构耦合到集成电路（IC）器件的互连堆叠的第一上互连层。 MOM电容器结构包括互连叠层的下互连层。 CBC结构还包括耦合到MOM电容器结构的互连叠层的第二上互连层。 CBC结构还包括在第一上部互连层和第二上部互连层之间的金属绝缘体金属（MIM）电容器层。 此外，CBC结构还包括耦合到MOM电容器结构的MIM电容器结构。 MIM电容器结构包括具有第一上部互连层的一部分的第一电容器板和具有MIM电容器层的一部分的第二电容器板。

公开(公告)号：US20230072667A1

公开(公告)日：2023-03-09

申请号：US17470274

申请日：2021-09-09

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong ZHU ,  Lixin GE ,  Giridhar NALLAPATI

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768

Abstract: Disclosed are examples of a device and method of fabricating a device including a first top contact, a second top contact, adjacent the first top contact, a first mesa disposed below the first top contact and a second mesa disposed below the second top contact. A first plate of a metal-insulator-metal (MIM) capacitor is disposed below the first top contact and electrically coupled to the first top contact. A first insulator of the MIM capacitor is disposed on the first plate. A second plate of the MIM capacitor is disposed on the first insulator and electrically coupled to the second top contact. A second insulator of the MIM capacitor is disposed on the second plate. A third plate of the MIM capacitor is disposed on the second insulator and electrically coupled to the first top contact.

公开(公告)号：US20180366592A1

公开(公告)日：2018-12-20

申请号：US15686827

申请日：2017-08-25

Applicant: QUALCOMM Incorporated

Inventor： Ye LU ,  Yun YUE ,  Chuan-Hsing CHEN ,  Bin YANG ,  Lixin GE ,  Ken LIAO

IPC: H01L29/93 ,  H01L29/66 ,  H01L29/423 ,  H01L29/45

CPC classification number: H01L29/93 ,  H01L23/4824 ,  H01L23/485 ,  H01L23/66 ,  H01L29/4232 ,  H01L29/456 ,  H01L29/66174 ,  H01L29/66181

Abstract: A short-channel metal oxide semiconductor varactor may include a source region of a first polarity having a source via contact. The varactor may further include a drain region of the first polarity having a drain via contact. The varactor may further include a channel region of the first polarity between the source region and the drain region. The channel region may include a gate. The varactor may further include at least one self-aligned contact (SAC) on the gate and between the source via contact and the drain via contact.

公开(公告)号：US20180342513A1

公开(公告)日：2018-11-29

申请号：US15663602

申请日：2017-07-28

Applicant: QUALCOMM Incorporated

Inventor： Ye LU ,  Junjing BAO ,  Bin YANG ,  Lixin GE ,  Yun YUE

IPC: H01L27/092 ,  H01L29/04 ,  H01L21/78 ,  H01L29/16 ,  H01L29/423 ,  H01L29/49 ,  H01L29/06 ,  H01L21/8238

Abstract: A complementary metal-oxide-semiconductor (CMOS) transistor may include a first semiconductor structure and a gate stack on the first semiconductor structure. The gate stack may include a gate dielectric layer on the first semiconductor structure, a work function material on the gate dielectric layer, and a gate metal fill material on the work function material of the gate stack. The gate metal fill material may include a low resistivity carbon alloy. A dielectric fill material may be included on the gate stack.