公开(公告)号：US20150303145A1

公开(公告)日：2015-10-22

申请号：US14255820

申请日：2014-04-17

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong ZHU ,  PR CHIDAMBARAM ,  Giridhar NALLAPATI ,  Choh Fei YEAP

IPC: H01L23/528 ,  H01L21/768 ,  G06F1/18

CPC classification number: H01L23/5283 ,  G06F1/18 ,  H01L21/76895 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The disclosure relates to a locally optimized integrated circuit (IC) including a first portion employing one or more metal interconnects having a first metal width and/or one or more vias having a first via width, and a second portion employing one or more metal interconnects having a second metal width and/or one or more vias having a second via width, wherein the second portion comprises a critical area of the IC, and wherein the second metal width is greater than the first metal width and the second via width is greater than the first via width. A method of locally optimizing an IC includes forming the one or more metal interconnects and/or the one or more vias in the first portion of the IC, and forming the one or more metal interconnects and/or the one or the more vias in the second portion of the integrated circuit.

Abstract translation: 本公开涉及局部优化的集成电路（IC），其包括使用具有第一金属宽度的一个或多个金属互连件的第一部分和/或具有第一通孔宽度的一个或多个通孔，以及采用一个或多个金属互连的第二部分 具有第二金属宽度和/或具有第二通孔宽度的一个或多个通孔，其中所述第二部分包括所述IC的临界区域，并且其中所述第二金属宽度大于所述第一金属宽度，并且所述第二通孔宽度更大 比第一个通道宽度。 局部优化IC的方法包括在IC的第一部分中形成一个或多个金属互连和/或一个或多个通孔，以及形成一个或多个金属互连和/或一个或多个通孔 集成电路的第二部分。

公开(公告)号：US20150001631A1

公开(公告)日：2015-01-01

申请号：US14109203

申请日：2013-12-17

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Ming CAI ,  Samit SENGUPTA ,  PR CHIDAMBARAM

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/8238 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/092

Abstract: Complementary metal oxide semiconductor (CMOS) devices include input/output (I/O) devices and core function devices. A method includes forming first conduction type wells for the I/O devices and the core function devices with a well mask. Such a method also includes creating at least one baseline device of a first conduction type, at least one first threshold voltage device of the first conduction type, and at least one second threshold device of the first conduction type by tuning a conduction type drive current ratio with a threshold voltage mask. The method also includes controlling a gate critical dimension for the first conduction type devices and/or at least one second conduction type device using a gate mask.

Abstract translation: 互补金属氧化物半导体（CMOS）器件包括输入/​​输出（I / O）器件和核心功能器件。 一种方法包括用于具有良好掩模的I / O设备和核心功能设备的第一导电型阱。 这种方法还包括通过调谐传导类型的驱动电流比率来产生第一导电类型的至少一个基线装置，第一导电类型的至少一个第一阈值电压装置和第一导电类型的至少一个第二阈值装置 具有阈值电压掩模。 该方法还包括使用栅极掩模来控制第一导电类型器件和/或至少一个第二导电型器件的栅极临界尺寸。

公开(公告)号：US20150028452A1

公开(公告)日：2015-01-29

申请号：US14512191

申请日：2014-10-10

Applicant: QUALCOMM INCORPORATED

Inventor： John J. ZHU ,  Bin YANG ,  PR CHIDAMBARAM ,  Lixin GE ,  Jihong CHOI

IPC: H01L23/522 ,  H01L49/02

CPC classification number: H01L23/538 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A complementary back end of line (BEOL) capacitor (CBC) structure includes a metal oxide metal (MOM) capacitor structure. The MOM capacitor structure is coupled to a first upper interconnect layer of an interconnect stack of an integrated circuit (IC) device. The MOM capacitor structure includes a lower interconnect layer of the interconnect stack. The CBC structure also includes a second upper interconnect layer of the interconnect stack coupled to the MOM capacitor structure. The CBC structure also includes a metal insulator metal (MIM) capacitor layer between the first upper interconnect layer and the second upper interconnect layer. In addition, CBC structure also includes a MIM capacitor structure coupled to the MOM capacitor structure. The MIM capacitor structure includes a first capacitor plate having a portion of the first upper interconnect layer, and a second capacitor plate having a portion of the MIM capacitor layer(s).

Abstract translation: 互补的后端（BEOL）电容器（CBC）结构包括金属氧化物金属（MOM）电容器结构。 MOM电容器结构耦合到集成电路（IC）器件的互连堆叠的第一上互连层。 MOM电容器结构包括互连叠层的下互连层。 CBC结构还包括耦合到MOM电容器结构的互连叠层的第二上互连层。 CBC结构还包括在第一上部互连层和第二上部互连层之间的金属绝缘体金属（MIM）电容器层。 此外，CBC结构还包括耦合到MOM电容器结构的MIM电容器结构。 MIM电容器结构包括具有第一上部互连层的一部分的第一电容器板和具有MIM电容器层的一部分的第二电容器板。