公开(公告)号：US20200098920A1

公开(公告)日：2020-03-26

申请号：US16140054

申请日：2018-09-24

Applicant: QUALCOMM Incorporated

Inventor： Fadoua CHAFIK ,  Samit SENGUPTA

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/04 ,  H01L21/8234

Abstract: A transistor gate structure includes a gate having gate sidewalls, a first side, and a second side opposite the first side. The first side may be coupled to a gate oxide layer, while the second side couples to an external device. The transistor structure also includes an inner gate spacer on the sidewalls of the gate, an outer gate spacer, and a middle gate spacer between the inner gate spacer and the outer gate spacer.

公开(公告)号：US20160093511A1

公开(公告)日：2016-03-31

申请号：US14496365

申请日：2014-09-25

Applicant: QUALCOMM Incorporated

Inventor： Samit SENGUPTA ,  Shashank EKBOTE ,  Da YANG ,  Choh Fei YEAP

IPC: H01L21/3213 ,  H01L21/762 ,  H01L27/088

CPC classification number: H01L21/32139 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886

Abstract: A multigate transistor device such as a fin-shaped field effect transistor (FinFET) is fabricated by applying a self-aligned diffusion break (SADB) mask having an opening positioned to expose an area of at least one portion of at least one gate stripe designated as at least one tie-off gate in the multigate transistor device and removing the tie-off gate through the opening of the SADB mask to isolate transistors adjacent to the tie-off gate.

Abstract translation: 通过施加具有开口的自对准扩散断裂（SADB）掩模来制造诸如鳍状场效应晶体管（FinFET）的多栅晶体管器件，所述掩模被定位成暴露指定的至少一个栅极条的至少一部分的区域 作为多栅极晶体管器件中的至少一个截止栅极，并且通过SADB掩模的开口去除关断栅极，以隔离与截止栅极相邻的晶体管。

公开(公告)号：US20150001631A1

公开(公告)日：2015-01-01

申请号：US14109203

申请日：2013-12-17

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Ming CAI ,  Samit SENGUPTA ,  PR CHIDAMBARAM

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/8238 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/092

Abstract: Complementary metal oxide semiconductor (CMOS) devices include input/output (I/O) devices and core function devices. A method includes forming first conduction type wells for the I/O devices and the core function devices with a well mask. Such a method also includes creating at least one baseline device of a first conduction type, at least one first threshold voltage device of the first conduction type, and at least one second threshold device of the first conduction type by tuning a conduction type drive current ratio with a threshold voltage mask. The method also includes controlling a gate critical dimension for the first conduction type devices and/or at least one second conduction type device using a gate mask.

Abstract translation: 互补金属氧化物半导体（CMOS）器件包括输入/​​输出（I / O）器件和核心功能器件。 一种方法包括用于具有良好掩模的I / O设备和核心功能设备的第一导电型阱。 这种方法还包括通过调谐传导类型的驱动电流比率来产生第一导电类型的至少一个基线装置，第一导电类型的至少一个第一阈值电压装置和第一导电类型的至少一个第二阈值装置 具有阈值电压掩模。 该方法还包括使用栅极掩模来控制第一导电类型器件和/或至少一个第二导电型器件的栅极临界尺寸。

公开(公告)号：US20200251473A1

公开(公告)日：2020-08-06

申请号：US16269065

申请日：2019-02-06

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Kwanyong LIM ,  Samit SENGUPTA

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/033

Abstract: Certain aspects of the present disclosure generally relate to a fin-slab field-effect transistor (FET). For example, certain aspects provide a semiconductor device having a substrate, a well region disposed above the substrate, a first fin disposed above the first well region, and a second fin disposed above the first well region and adjacent to the first fin. In certain aspects, a dielectric region is disposed between the second fin and the first well region, and a first gate region is disposed adjacent to the first fin and the second fin.

公开(公告)号：US20200166566A1

公开(公告)日：2020-05-28

申请号：US16203042

申请日：2018-11-28

Applicant: QUALCOMM Incorporated

Inventor： Samit SENGUPTA ,  Fadoua CHAFIK

IPC: G01R31/28 ,  G01R31/3185

Abstract: An integrated circuit test structure has a first set of unit cells in a first conductive layer. The first set of unit cells has a first portion to receive a charge of a first polarity and a second portion to receive a charge of a second polarity. The first portion is electrically independent of the second portion. The first portion has branched conductive lines interdigitated with branched conductive lines of the second portion. The integrated circuit test structure also has a second set of unit cells in the first conductive layer. The second set of unit cells are transposed relative to the first set of unit cells.

公开(公告)号：US20200027801A1

公开(公告)日：2020-01-23

申请号：US16248579

申请日：2019-01-15

Applicant: QUALCOMM Incorporated

Inventor： Fadoua CHAFIK ,  Samit SENGUPTA

IPC: H01L21/66 ,  H01L23/522 ,  H01L23/528 ,  H01L21/311 ,  H01L21/768

Abstract: A integrated circuit structure has a first test structure with a first set of un-landed vias. The first set of un-landed vias has a first side for each of the first set of un-landed vias proximate to a first BEOL layer (first back-end-of-line layer) of a chip and spaced apart, by a first gap, from the first BEOL layer. Each of the first set of un-landed vias has a first depth that is smaller than a landed depth of a chip via conductively connecting the first BEOL layer to a second BEOL layer of the chip. The first set of un-landed vias also has a second side for each of the first set of un-landed vias opposite the first side and connected to the second BEOL layer.