公开(公告)号：US20200098920A1

公开(公告)日：2020-03-26

申请号：US16140054

申请日：2018-09-24

Applicant: QUALCOMM Incorporated

Inventor： Fadoua CHAFIK ,  Samit SENGUPTA

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/04 ,  H01L21/8234

Abstract: A transistor gate structure includes a gate having gate sidewalls, a first side, and a second side opposite the first side. The first side may be coupled to a gate oxide layer, while the second side couples to an external device. The transistor structure also includes an inner gate spacer on the sidewalls of the gate, an outer gate spacer, and a middle gate spacer between the inner gate spacer and the outer gate spacer.

公开(公告)号：US20230345692A1

公开(公告)日：2023-10-26

申请号：US17660758

申请日：2022-04-26

Applicant: QUALCOMM Incorporated

Inventor： Fadoua CHAFIK ,  Xiaochen ZHANG

IPC: H01L27/11 ,  H01L29/66

CPC classification number: H01L27/1108 ,  H01L29/6653

Abstract: Disclosed are apparatuses and techniques for fabricating an apparatus including a semiconductor device. The semiconductor device may include one or more static random-access memory (SRAM) transistors, each including a first gate spacer structure; one or more logic nominal transistors, each including a second gate spacer structure; and one or more logic gate-biased transistors, each including a third gate spacer structure, where the third gate spacer structure is thinner than the first gate spacer structure and where the one or more SRAM transistors, the one or more logic nominal transistors, and the one or more logic gate-biased transistors each have a same contacted poly pitch (CPP).

公开(公告)号：US20200256915A1

公开(公告)日：2020-08-13

申请号：US16274158

申请日：2019-02-12

Applicant: QUALCOMM Incorporated

Inventor： Youn Sung CHOI ,  Fadoua CHAFIK ,  Kwanyong LIM

IPC: G01R31/28 ,  H01L23/48 ,  H03K19/0185 ,  H01L21/66 ,  H01L27/092

Abstract: An on-chip test structure has an NMOS transistor (N-type metal oxide semiconductor transistor). The NMOS transistor includes a first source/drain contact and a first gate contact formed in an N-type source/drain opening. The on-chip test structure also has a PMOS transistor (P-type metal oxide semiconductor transistor) adjacent to the NMOS transistor. The PMOS transistor includes a second source/drain contact and a second gate contact formed in a P-type source/drain opening. A distance between the N-type source/drain opening and the P-type source/drain opening is offset relative to a distance between other N-type source/drain openings and P-type source/drain openings, outside the on-chip test structure, that are configured according to a standard technology specification.

公开(公告)号：US20200166566A1

公开(公告)日：2020-05-28

申请号：US16203042

申请日：2018-11-28

Applicant: QUALCOMM Incorporated

Inventor： Samit SENGUPTA ,  Fadoua CHAFIK

IPC: G01R31/28 ,  G01R31/3185

Abstract: An integrated circuit test structure has a first set of unit cells in a first conductive layer. The first set of unit cells has a first portion to receive a charge of a first polarity and a second portion to receive a charge of a second polarity. The first portion is electrically independent of the second portion. The first portion has branched conductive lines interdigitated with branched conductive lines of the second portion. The integrated circuit test structure also has a second set of unit cells in the first conductive layer. The second set of unit cells are transposed relative to the first set of unit cells.

公开(公告)号：US20200027801A1

公开(公告)日：2020-01-23

申请号：US16248579

申请日：2019-01-15

Applicant: QUALCOMM Incorporated

Inventor： Fadoua CHAFIK ,  Samit SENGUPTA

IPC: H01L21/66 ,  H01L23/522 ,  H01L23/528 ,  H01L21/311 ,  H01L21/768

Abstract: A integrated circuit structure has a first test structure with a first set of un-landed vias. The first set of un-landed vias has a first side for each of the first set of un-landed vias proximate to a first BEOL layer (first back-end-of-line layer) of a chip and spaced apart, by a first gap, from the first BEOL layer. Each of the first set of un-landed vias has a first depth that is smaller than a landed depth of a chip via conductively connecting the first BEOL layer to a second BEOL layer of the chip. The first set of un-landed vias also has a second side for each of the first set of un-landed vias opposite the first side and connected to the second BEOL layer.