GATE SPACER STRUCTURE
    1.
    发明公开

    公开(公告)号:US20230345692A1

    公开(公告)日:2023-10-26

    申请号:US17660758

    申请日:2022-04-26

    CPC classification number: H01L27/1108 H01L29/6653

    Abstract: Disclosed are apparatuses and techniques for fabricating an apparatus including a semiconductor device. The semiconductor device may include one or more static random-access memory (SRAM) transistors, each including a first gate spacer structure; one or more logic nominal transistors, each including a second gate spacer structure; and one or more logic gate-biased transistors, each including a third gate spacer structure, where the third gate spacer structure is thinner than the first gate spacer structure and where the one or more SRAM transistors, the one or more logic nominal transistors, and the one or more logic gate-biased transistors each have a same contacted poly pitch (CPP).

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