公开(公告)号：US20170373175A1

公开(公告)日：2017-12-28

申请号：US15192773

申请日：2016-06-24

Applicant: QUALCOMM Incorporated

Inventor： Shiqun GU ,  Gengming TAI ,  Je-Hsiung LAN ,  Matthew Michael NOWAK ,  Miguel MIRANDA CORBALAN ,  Steve FANELLI

IPC: H01L29/737 ,  H01L23/31 ,  H01L29/08 ,  H01L29/66

Abstract: Disclosed is a heterojunction bipolar transistor, and method of manufacturing the same, including an emitter having a conductive emitter contact coupled to a first side of the emitter, a first side of a base coupled to a second side of the emitter opposite the first side of the emitter, a collector coupled to the base on a second side of the base opposite the emitter, wherein an area of a junction between the base and the collector is less than or equal to an area of a junction between the base and the emitter, a first conductive base contact coupled to the base, and a conductive collector contact coupled to the collector on the side of the collector opposite the emitter and substantially parallel to the first conductive base contact.

公开(公告)号：US20220344249A1

公开(公告)日：2022-10-27

申请号：US17242083

申请日：2021-04-27

Applicant: QUALCOMM Incorporated

Inventor： Biancun XIE ,  Shree Krishna PANDEY ,  Irfan KHAN ,  Miguel MIRANDA CORBALAN ,  Stanley Seungchul SONG

IPC: H01L23/498 ,  H01L25/065 ,  H01L21/48

Abstract: A three-dimensional (3D) integrated circuit (IC) includes a first die. The first die includes a 3D stacked capacitor on a first surface of the first die and coupled to a power distribution network (PDN) of the first die. The 3D IC also includes a second die stacked on the first surface of the first die, proximate the 3D stacked capacitor on the first surface of the first die. The 3D IC further includes active circuitry coupled to the 3D stacked capacitor through the PDN of the first die.

公开(公告)号：US20240363605A1

公开(公告)日：2024-10-31

申请号：US18454388

申请日：2023-08-23

Applicant: QUALCOMM Incorporated

Inventor： Darko POPOVIC ,  Miguel MIRANDA CORBALAN ,  Durodami LISK ,  Yue LI ,  Irfan KHAN

IPC: H01L25/16 ,  H01L23/00

CPC classification number: H01L25/16 ,  H01L24/16 ,  H01L24/17 ,  H01L23/3107 ,  H01L23/481 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16265 ,  H01L2224/17181 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19105

Abstract: A stacked integrated circuit (IC) device includes a first die including active circuitry and a power distribution network (PDN). The first die has a first set of contacts on a first side of the first die. The stacked IC device also includes a second die coupled, on a first side of the second die, to the first side of the first die. The second die also includes, on a second side of the second die, a second set of contacts to electrically connect circuitry of the second die to a substrate. The stacked IC device also includes an integrated capacitor device (ICD) coupled to the first side of the first die. The ICD is electrically connected, via the first set of contacts, to the PDN and includes one or more through-ICD conductors to electrically connect the PDN to the substrate.

公开(公告)号：US20180240898A1

公开(公告)日：2018-08-23

申请号：US15614471

申请日：2017-06-05

Applicant: QUALCOMM Incorporated

Inventor： Gengming TAO ,  Bin YANG ,  Xia LI ,  Miguel MIRANDA CORBALAN

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7371 ,  H01L29/0696 ,  H01L29/0813 ,  H01L29/0817 ,  H01L29/1004 ,  H01L29/42304 ,  H01L29/66242

Abstract: A heterojunction bipolar transistor unit cell may include a compound semiconductor substrate. The heterojunction bipolar transistor unity may also include a base mesa on the compound semiconductor substrate. The base mesa may include a collector region on the compound semiconductor substrate and a base region on the collector region. The heterojunction bipolar transistor unity may further include a single emitter mesa on the base mesa.