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    IO INTERCONNECT CAGE STRUCTURE FOR PACKAGE FORM REDUCTION
    1.
    发明申请
    IO INTERCONNECT CAGE STRUCTURE FOR PACKAGE FORM REDUCTION 有权

    公开(公告)号：US20250096094A1

    公开(公告)日：2025-03-20

    申请号：US18468474

    申请日：2023-09-15

    Applicant: QUALCOMM Incorporated

    Inventor： Aniket PATIL ,  Piyush GUPTA ,  Durodami LISK

    IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H05K1/18

    Abstract: Disclosed are package devices that include interconnects on first and second surfaces of a package substrate. The interconnects on the first surface of the package substrate are configured to carry general purpose input-output (GPIO) and miscellaneous IO signals. The interconnects on the second surface of the package substrate are configured to carry high speed input-output (HSIO) signals-signals whose speeds are above some minimum speed threshold. In this way, the package form can be reduced while still allowing for increased number of IO signals to be delivered.

    PACKAGE WITH A SUBSTRATE COMPRISING EMBEDDED STACKED TRENCH CAPACITOR DEVICES
    2.
    发明公开
    PACKAGE WITH A SUBSTRATE COMPRISING EMBEDDED STACKED TRENCH CAPACITOR DEVICES 审中-公开

    公开(公告)号：US20240038831A1

    公开(公告)日：2024-02-01

    申请号：US17878758

    申请日：2022-08-01

    Applicant: QUALCOMM Incorporated

    Inventor： Ryan LANE ,  Charles David PAYNTER ,  Durodami LISK ,  Darko POPOVIC ,  Yue LI ,  Shree Krishna PANDEY

    IPC: H01L49/02 ,  H01L23/522

    CPC classification number: H01L28/91 ,  H01L23/5223 ,  H01L24/16

    Abstract: A package comprising a substrate and an integrated device. The substrate includes a core layer comprising a first surface and a second surface; a plurality of core interconnects located in the core layer; at least one first dielectric layer coupled to the first surface of the core layer; a first plurality of interconnects located in the at least one first dielectric layer; at least one second dielectric layer coupled to the second surface of the core layer; a second plurality of interconnects located in the at least one second dielectric layer; and a capacitor structure located in the core layer. The capacitor structure includes a first trench capacitor device comprising a first front side and a first back side; and a second trench capacitor device coupled to the first trench capacitor device, where the second trench capacitor device comprises a second front side and a second back side.

    STACKED INTEGRATED CIRCUIT DEVICES
    3.
    发明申请
    STACKED INTEGRATED CIRCUIT DEVICES 有权

    公开(公告)号：US20250062285A1

    公开(公告)日：2025-02-20

    申请号：US18451971

    申请日：2023-08-18

    Applicant: QUALCOMM Incorporated

    Inventor： Yue LI ,  Ryan LANE ,  Yangyang SUN ,  Charles David PAYNTER ,  Durodami LISK

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/16

    Abstract: A stacked integrated circuit (IC) device includes a first die having a first face, a first active region adjacent to the first face, and first die-interconnect contacts disposed on the first face and connected to first circuitry. The stacked IC device includes a second die having a second face, a second active region adjacent to the second face, and second die-interconnect contacts disposed on the second face and connected to second circuitry. The first face is oriented toward the second face, and the first die-interconnect contacts are connected to the second die-interconnect contacts. The stacked IC device includes a set of redistribution layers electrically connected to redistribution contacts on the first face, the second face, or both. The stacked IC device also includes interconnect conductors connected to the redistribution layers to provide signal paths from the first die, the second die, or both, to a set of external contacts.

    PACKAGE COMPRISING A BRIDGE LOCATED BETWEEN METALLIZATION PORTIONS
    6.
    发明申请
    PACKAGE COMPRISING A BRIDGE LOCATED BETWEEN METALLIZATION PORTIONS 有权

    公开(公告)号：US20250096207A1

    公开(公告)日：2025-03-20

    申请号：US18470344

    申请日：2023-09-19

    Applicant: QUALCOMM Incorporated

    Inventor： Yue LI ,  Durodami LISK ,  Ryan LANE ,  Darko POPOVIC

    IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538

    Abstract: A package comprising a first metallization portion; a first integrated device coupled to the first metallization portion; a bridge coupled to the first metallization portion; an encapsulation layer coupled to the first metallization portion; a second metallization portion coupled to the bridge and the encapsulation layer, such that the first integrated device, the bridge and the encapsulation layer are located between the first metallization portion and the second metallization portion, and a second integrated device coupled to the second metallization portion, wherein the second integrated device and the bridge at least partially vertically overlap.

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