公开(公告)号：US20190280125A1

公开(公告)日：2019-09-12

申请号：US16423472

申请日：2019-05-28

Applicant: QUALCOMM Incorporated

Inventor： Narasimhulu KANIKE ,  Qingqing LIANG ,  Fabio Alessio MARINO ,  Francesco CAROBOLANTE

IPC: H01L29/78 ,  H01L29/93 ,  H01L27/092 ,  H01L23/522 ,  H01L29/06 ,  H01L29/66 ,  H01L23/528 ,  H01L27/08

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device and techniques for fabricating a semiconductor device. In certain aspects, the semiconductor device includes a fin, a first non-insulative region disposed adjacent to a first side of the fin, and a second non-insulative region disposed adjacent to a second side of the fin. In certain aspects, the first non-insulative region and the second non-insulative region are separated by a trench, at least a portion of the trench being filled with a dielectric material disposed around the fin.

公开(公告)号：US20180342620A1

公开(公告)日：2018-11-29

申请号：US15602915

申请日：2017-05-23

Applicant: QUALCOMM Incorporated

Inventor： Narasimhulu KANIKE ,  Qingqing LIANG ,  Fabio Alessio MARINO ,  Francesco CAROBOLANTE

IPC: H01L29/78 ,  H01L23/522 ,  H01L23/528 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7851 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/0805 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/93

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device and techniques for fabricating a semiconductor device. In certain aspects, the semiconductor device includes a fin, a first non-insulative region disposed adjacent to a first side of the fin, and a second non-insulative region disposed adjacent to a second side of the fin. In certain aspects, the first non-insulative region and the second non-insulative region are separated by a trench, at least a portion of the trench being filled with a dielectric material disposed around the fin.

公开(公告)号：US20190312152A1

公开(公告)日：2019-10-10

申请号：US15946628

申请日：2018-04-05

Applicant: QUALCOMM Incorporated

Inventor： Fabio Alessio MARINO ,  Sinan GOKTEPELI ,  Narasimhulu KANIKE ,  Qingqing LIANG ,  Paolo MENEGOLI ,  Francesco CAROBOLANTE ,  Aristotele HADJICHRISTOS

IPC: H01L29/93 ,  H01L27/12 ,  H01L29/36

Abstract: Certain aspects of the present disclosure provide semiconductor variable capacitors. One example semiconductor variable capacitor generally includes a semiconductor region, a first insulator region disposed below the semiconductor region, a first non-insulative region disposed below the first insulator region, a second non-insulative region disposed adjacent to the semiconductor region, and a third non-insulative region disposed adjacent to the semiconductor region, wherein the semiconductor region is disposed between the second non-insulative region and the third non-insulative region. In certain aspects, the semiconductor variable capacitor may include a second insulator region disposed above the semiconductor region and a second semiconductor region disposed above the second insulator region.

公开(公告)号：US20180083473A1

公开(公告)日：2018-03-22

申请号：US15268042

申请日：2016-09-16

Applicant: QUALCOMM Incorporated

Inventor： Paolo MENEGOLI ,  Linda IRISH ,  Fabio Alessio MARINO

IPC: H02J7/02 ,  H02J7/00 ,  H02J5/00

CPC classification number: H02J7/025 ,  H02J3/01 ,  H02J5/005 ,  H02J7/0052 ,  H02J50/12 ,  H02M1/44 ,  Y02E40/40

Abstract: Techniques for tuning a resonant network are discussed. An example apparatus for controlling an output parameter with a resonant network comprising a differential-series circuit with a first variable reactive element on a first branch of the differential-series circuit and a second variable reactive element on a second branch of the differential-series circuit, such that the resonant network is coupled to an output circuit. The apparatus includes a common control element operably coupled to the first variable reactive element and the second variable reactive element, and a control circuit operably coupled to the output circuit and the common control element and configured to vary an impedance of the resonant network based on a value of the output parameter in the output circuit.

公开(公告)号：US20180083472A1

公开(公告)日：2018-03-22

申请号：US15267597

申请日：2016-09-16

Applicant: QUALCOMM Incorporated

Inventor： Paolo MENEGOLI ,  Francesco CAROBOLANTE ,  Fabio Alessio MARINO

IPC: H02J7/02 ,  H02J7/04 ,  H02J50/12

CPC classification number: H02J7/025 ,  H01G7/06 ,  H02J7/045 ,  H02J7/345 ,  H02J50/12 ,  H02J50/80 ,  H02J50/90 ,  Y02T10/7022

Abstract: Techniques for controlling a resonant network are disclosed. An example of an apparatus for varying capacitance in a resonant network includes a variable capacitor circuit configured to vary a capacitance in response to a control signal, at least one biasing component operably coupled to the variable capacitor circuit, and a control circuit configured to generate the control signal, such that the control signal includes a first tuning value corresponding to a first capacitance value, and output the control signal at the first tuning value to reduce an impedance of the at least one biasing component and vary the capacitance of the variable capacitor circuit, such that the impedance of the at least one biasing component subsequently increases when the first capacitance value is realized.

公开(公告)号：US20180240915A1

公开(公告)日：2018-08-23

申请号：US15438400

申请日：2017-02-21

Applicant: QUALCOMM Incorporated

Inventor： Fabio Alessio MARINO ,  Paolo MENEGOLI ,  Narasimhulu KANIKE ,  Francesco CAROBOLANTE

IPC: H01L29/93 ,  H01L27/08 ,  H01L27/12

CPC classification number: H01L29/93 ,  H01L27/0808 ,  H01L27/1203 ,  H01L29/94

Abstract: Certain aspects of the present disclosure generally relate to techniques for adjusting or setting a capacitance-versus-voltage (C-V) characteristic of a variable capacitor. For example, certain aspects of the present disclosure provide a capacitor device. The capacitor device generally includes a first variable capacitor and a second variable capacitor, each comprising a first terminal and a second terminal. In certain aspects, the second terminal of the second variable capacitor is coupled to the first terminal of the first variable capacitor, and the first terminal of the first variable capacitor is coupled to at least one biasing voltage node. In some cases, a decoupling capacitor may be coupled to the first terminal of the first variable capacitor.

公开(公告)号：US20180233605A1

公开(公告)日：2018-08-16

申请号：US15850118

申请日：2017-12-21

Applicant: QUALCOMM Incorporated

Inventor： Fabio Alessio MARINO ,  Paolo MENEGOLI ,  Narasimhulu KANIKE ,  Francesco CAROBOLANTE ,  Qingqing LIANG

IPC: H01L29/93 ,  H01L21/285 ,  H01L21/28 ,  H01L29/66 ,  H01L29/45 ,  H01L29/49

CPC classification number: H01L29/93 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66174 ,  H01L29/66189

Abstract: Certain aspects of the present disclosure provide a semiconductor variable capacitor. The semiconductor variable capacitor generally includes a first non-insulative region disposed above a semiconductor region, and a second non-insulative region disposed adjacent to the semiconductor region. In certain aspects, the semiconductor variable capacitor also includes a first silicide layer disposed above the second non-insulative region, wherein the first silicide layer overlaps at least a portion of the semiconductor region. In certain aspects, a control region may be disposed adjacent to the semiconductor region such that a capacitance between the first non-insulative region and the second non-insulative region is configured to be adjusted by varying a control voltage applied to the control region.

公开(公告)号：US20180102427A1

公开(公告)日：2018-04-12

申请号：US15840961

申请日：2017-12-13

Applicant: QUALCOMM Incorporated

Inventor： Fabio Alessio MARINO ,  Paolo MENEGOLI

IPC: H01L29/778 ,  H01L29/78 ,  H01L29/40 ,  H01L29/423 ,  H01L29/417

CPC classification number: H01L29/7787 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41775 ,  H01L29/42316 ,  H01L29/7831 ,  H01L29/7835 ,  H01L29/7838

Abstract: A novel semiconductor power transistor is presented. The semiconductor structure is simple and is based on a MOS configuration with a drift region and an additional gate that modulates the carrier density in the drift region, so that the control on the carrier transport is enhanced and the specific on-resistance per area is reduced. This characteristic enables the use of short gate lengths while maintaining the electric field under the gate within reasonable values in high voltage applications, without increasing the device on-resistance. It offers the advantage of extremely lower on-resistance for the same silicon area while improving on its dynamic performances with respect to the standard CMOS technology. Another inherent advantage is that the switching gate losses are smaller due to lower VGS voltages required to operate the device.

公开(公告)号：US20190326448A1

公开(公告)日：2019-10-24

申请号：US15957484

申请日：2018-04-19

Applicant: QUALCOMM Incorporated

Inventor： Sinan GOKTEPELI ,  Fabio Alessio MARINO ,  Narasimhulu KANIKE ,  Plamen Vassilev KOLEV ,  Qingqing LIANG ,  Paolo MENEGOLI ,  Francesco CAROBOLANTE ,  Aristotele HADJICHRISTOS

IPC: H01L29/93 ,  H01L29/45 ,  H01L29/06

Abstract: Certain aspects of the present disclosure provide a semiconductor device. One example semiconductor device generally includes a semiconductor region, an insulative layer, a first terminal, and a first non-insulative region coupled to the first terminal, the insulative layer being disposed between the first non-insulative region and the semiconductor region. In certain aspects, the insulative layer is disposed adjacent to a first side of the semiconductor region. In certain aspects, the semiconductor device also includes a second terminal, and a first silicide layer coupled to the second terminal and disposed adjacent to a second side of the semiconductor region, the first side and the second side being opposite sides of the semiconductor region.

公开(公告)号：US20190305143A1

公开(公告)日：2019-10-03

申请号：US15937021

申请日：2018-03-27

Applicant: QUALCOMM Incorporated

Inventor： Fabio Alessio MARINO ,  Narasimhulu KANIKE ,  Qingqing LIANG ,  Francesco CAROBOLANTE ,  Paolo MENEGOLI

IPC: H01L29/94 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66

Abstract: In certain aspects, a variable capacitor comprises a well having a first side and a second side, an N+ diffusion abutted the well at the first side, a P+ diffusion abutted the well at the second side, and an insulator on the well. The variable capacitor further comprises a gate plate on the insulator having a first gate segment and a second gate segment, wherein the first gate segment and the second gate segment are configured to have different work functions.