公开(公告)号：US10121703B2

公开(公告)日：2018-11-06

申请号：US15789972

申请日：2017-10-21

申请人： International Business Machines Corporation

发明人： Veeraraghavan S. Basker ,  Alexander Reznicek

IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/324 ,  H01L21/265 ,  H01L21/02 ,  H01L29/08 ,  H01L21/8252 ,  H01L29/20 ,  H01L27/088 ,  H01L21/225 ,  H01L29/417 ,  H01L21/322 ,  H01L21/8258

摘要： FinFET devices including III-V fin structures and silicon-based source/drain regions are formed on a semiconductor substrate. Silicon is diffused into the III-V fin structures to form n-type junctions. Leakage through the substrate is addressed by forming p-n junctions adjoining the source/drain regions and isolating the III-V fin structures under the channel regions.

公开(公告)号：US20180309015A1

公开(公告)日：2018-10-25

申请号：US15868755

申请日：2018-01-11

申请人： Changzhou Shichuang Energy Technology Co., Ltd.

发明人： Changrui REN ,  Liming FU

IPC分类号： H01L31/18 ,  H01L21/322 ,  H01L31/0368 ,  H01L31/0236

CPC分类号： H01L31/186 ,  H01L21/3221 ,  H01L31/02363 ,  H01L31/03682 ,  H01L31/1804 ,  Y02E10/50 ,  Y02P70/521

摘要： A method for eliminating metal composites from a polycrystalline silicon cell piece, comprising the steps of: injecting current into the polycrystalline silicon cell piece under a certain temperature by means of an electric injection method, thereby eliminating the metal composites from the interior of the polycrystalline silicon cell piece; the present invention discloses a simple process, a short processing-time, a low manufacturing cost, and can easily be scaled for manufacture.

公开(公告)号：US20180294379A1

公开(公告)日：2018-10-11

申请号：US16000510

申请日：2018-06-05

申请人： Lumileds LLC

发明人： Kwong-Hin Henry Choy

IPC分类号： H01L33/24 ,  H01L33/40 ,  H01L21/285 ,  H01L21/322 ,  H01L21/324 ,  H01L33/22 ,  H01L33/20 ,  H01L33/14 ,  H01L33/00 ,  H01L33/30 ,  H01L21/02

摘要： A device according to embodiments of the invention includes a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region. A surface of the p-type region perpendicular to a growth direction of the semiconductor structure includes a first portion and a second portion. The first portion is less conductive than the second portion. The device further includes a p-contact formed on the p-type region. The p-contact includes a reflector and a blocking material. The blocking material is disposed over the first portion and no blocking material is disposed over the second portion.

公开(公告)号：US10090417B2

公开(公告)日：2018-10-02

申请号：US14404827

申请日：2013-03-18

申请人： FUJI ELECTRIC CO., LTD.

发明人： Takashi Tsuji ,  Akimasa Kinoshita ,  Noriyuki Iwamuro ,  Kenji Fukuda

IPC分类号： H01L29/15 ,  H01L21/44 ,  H01L29/47 ,  H01L29/66 ,  H01L21/322 ,  H01L21/425 ,  H01L21/28 ,  H01L29/872 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L21/02 ,  H01L29/36

摘要： A p-type region, a p− type region, and a p+ type region are selectively disposed in a surface layer of a silicon carbide substrate base. The p-type region and the p− type region are disposed in a breakdown voltage structure portion that surrounds an active region. The p+ type region is disposed in the active region to make up a JBS structure. The p− type region surrounds the p-type region to make up a junction termination structure. A Schottky electrode forms a Schottky junction with an n-type silicon carbide epitaxial layer. The Schottky electrode overhangs an interlayer insulation film covering a portion of the p-type region and this overhanging portion acts as a field plate. The p+ type region has an acceptor concentration greater than or equal to a predetermined concentration and can make a forward surge current larger.

公开(公告)号：US20180248045A1

公开(公告)日：2018-08-30

申请号：US15724600

申请日：2017-10-04

申请人： Samsung Display Co., Ltd.

发明人： Junhyung LIM ,  Jaybum KIM ,  Kyoungseok SON ,  Jihun LIM

IPC分类号： H01L29/786 ,  H01L21/02 ,  H01L21/322 ,  H01L51/52 ,  H01L27/12 ,  H01L27/32 ,  H01L29/04 ,  H01L29/423

摘要： A semiconductor device may include a base substrate, a first thin-film transistor (“TFT”) provided on the base substrate, a second TFT provided on the base substrate, and a plurality of insulating layers provided on the base substrate to define at least one dummy hole that is not overlapped with the first and second TFTs. The first TFT may include a first input electrode, a first output electrode, a first control electrode, and a first semiconductor pattern including a crystalline semiconductor material, and the second TFT may include a second input electrode, a second output electrode, a second control electrode, and a second semiconductor pattern including an oxide semiconductor material. A shortest distance between the at least one dummy hole and the second semiconductor pattern may be equal to or shorter than 5 micrometers (μm), in a plan view.

公开(公告)号：US20180204735A1

公开(公告)日：2018-07-19

申请号：US15921249

申请日：2018-03-14

申请人： HITACHI KOKUSAI ELECTRIC INC.

发明人： Kazuhiro YUASA ,  Noriaki MICHITA

IPC分类号： H01L21/322 ,  H01L21/324 ,  H01L21/02 ,  H01L21/268 ,  H01L21/67

CPC分类号： H01L21/322 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02494 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02675 ,  H01L21/2686 ,  H01L21/324 ,  H01L21/67115 ,  H01L21/67248 ,  H01L21/67757

摘要： There is provide a technique that includes preparing a substrate, in which an insulating film is formed on a pattern having an aspect ratio of 20 or greater and a process target film having a thickness of 200 Å or smaller is formed on the insulating film, in a process chamber; raising a temperature of the substrate to a first temperature with an electromagnetic wave; crystallizing the process target film for a first process time period while maintaining the first temperature; raising the temperature of the substrate to a second temperature, which is higher than the first temperature, with the electromagnetic wave, after the act of crystallizing the process target film; and repairing a crystal defect of the crystallized process target film for a second process time period, which is shorter than the first process time period, while maintaining the second temperature.

公开(公告)号：US10020203B1

公开(公告)日：2018-07-10

申请号：US15399981

申请日：2017-01-06

申请人： SUMCO CORPORATION

发明人： Yasuo Koike ,  Tomokazu Katano ,  Toshiaki Ono

IPC分类号： H01L23/58 ,  H01L21/322 ,  H01L29/16 ,  H01L29/32 ,  H01L29/36 ,  H01L21/02 ,  C30B29/06 ,  C30B29/64 ,  C30B15/20

摘要： An epitaxial silicon wafer includes a silicon wafer consisting of a COP region in which a nitrogen concentration is 1×1012−1×1013 atoms/cm3, and an epitaxial silicon film formed on the silicon wafer. When heat treatment for evaluation is applied, a density of BMD formed inside the silicon wafer is 1×108−3×109 atoms/cm3 over the entire radial direction of the silicon wafer. An average density of the BMD formed in an outer peripheral region of the silicon wafer which is a 1-10 mm range separated inward from an outermost periphery thereof is lower than the average density of the BMD formed in a center region. A variation in the BMD density in the outer peripheral region is 3 or less, and a residual oxygen concentration in the outer peripheral region is 8×1017 atoms/cm3 or more.

公开(公告)号：US20180122639A1

公开(公告)日：2018-05-03

申请号：US15572769

申请日：2016-03-14

申请人： SHIN-ETSU HANDOTAI CO., LTD.

发明人： Norihiro KOBAYASHI ,  Osamu ISHIKAWA ,  Kenji MEGURO ,  Taishi WAKABAYASHI ,  Hiroyuki OONISHI

IPC分类号： H01L21/20 ,  H01L21/322 ,  H01L27/12 ,  H01L21/762

CPC分类号： H01L21/2007 ,  H01L21/02 ,  H01L21/3226 ,  H01L21/76254 ,  H01L27/12

摘要： A method for manufacturing a bonded SOI wafer, including depositing a polycrystalline silicon layer on a base wafer, forming an insulator film on a bond wafer, bonding the bond wafer and a polished surface of the silicon layer with the insulator film interposed, and thinning the bond wafer, wherein a silicon single crystal wafer having a resistivity of 100 Ω-cm or more is the base wafer, the step of depositing the silicon layer includes a stage of forming an oxide film on the surface of the base wafer, and the silicon layer is deposited between 1050° C. and 1200° C. Accordingly, the method enables a polycrystalline silicon layer to be deposited while preventing the progress of single crystallization even through a heat treatment step in the SOI wafer manufacturing process or a heat treatment step in the device manufacturing process and can improve throughput in the polycrystalline silicon layer depositing step.

公开(公告)号：US09939511B2

公开(公告)日：2018-04-10

申请号：US15514545

申请日：2015-09-16

申请人： SunEdison Semiconductor Limited (UEN201334164H)

发明人： Igor Rapoport ,  Robert James Crepin ,  Patrick Alan Taylor

IPC分类号： H01L21/66 ,  H01L21/322 ,  H01L21/324 ,  G01R31/26 ,  G01R31/28 ,  G01R35/00 ,  H01L21/265 ,  H01L29/167 ,  H01L29/36 ,  H01L21/266 ,  H01L29/207

CPC分类号： G01R35/007 ,  G01R31/2648 ,  G01R31/2831 ,  G01R35/005 ,  H01L21/26506 ,  H01L21/2654 ,  H01L21/266 ,  H01L21/3221 ,  H01L21/324 ,  H01L22/12 ,  H01L22/14 ,  H01L29/167 ,  H01L29/207 ,  H01L29/36

摘要： A method of preparing an iron-implanted semiconductor wafer for use in surface photovoltage iron mapping and other evaluation techniques. A semiconductor wafer is implanted with iron through the at least two different regions of the front surface of the semiconductor at different iron implantation densities, and the iron-implanted semiconductor wafer is annealed at a temperature and duration sufficient to diffuse implanted iron into the bulk region of the semiconductor wafer.

公开(公告)号：US09938640B2

公开(公告)日：2018-04-10

申请号：US15104358

申请日：2015-01-08

申请人： SHIN-ETSU HANDOTAI CO., LTD.

发明人： Ryoji Hoshi ,  Hiroyuki Kamada

IPC分类号： C30B15/14 ,  C30B33/02 ,  C30B29/06 ,  H01L21/322 ,  H01L29/32

CPC分类号： C30B33/02 ,  C30B29/06 ,  H01L21/3221 ,  H01L29/32

摘要： The present invention is a method for a heat treatment of a silicon single crystal wafer in an oxidizing ambient, including: performing the heat treatment based on a condition determined by a tripartite correlation between a heat treatment temperature during the heat treatment, an oxygen concentration in the silicon single crystal wafer before the heat treatment, and a void size in the silicon single crystal wafer before the heat treatment. This provides a method for a heat treatment of a silicon single crystal wafer which can annihilate void defects or micro oxide precipitate nuclei in a silicon single crystal wafer with low cost, efficiently, and securely by a heat treatment in an oxidizing ambient.