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    Semiconductor device
    1.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11424357B2

    公开(公告)日：2022-08-23

    申请号：US17159718

    申请日：2021-01-27

    Applicant: FUJI ELECTRIC CO., LTD.

    Inventor： Akimasa Kinoshita

    IPC: H01L29/78 ,  H01L29/16 ,  H01L29/167 ,  H01L29/06

    Abstract: A semiconductor device, including a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, provided on the semiconductor substrate and having an impurity concentration lower than that of the semiconductor substrate, a second semiconductor layer of a second conductivity type, selectively provided on the first semiconductor layer, a plurality of first semiconductor regions of the first conductivity type, selectively provided in the second semiconductor layer at a surface thereof, a plurality of gate insulating films in contact with the second semiconductor layer, a plurality of gate electrodes respectively provided on the gate insulating films, a plurality of first electrodes provided on the second semiconductor layer and the first semiconductor regions, and a second electrode provided on a back surface of the semiconductor substrate. The semiconductor substrate contains boron, a concentration of the boron therein being in a range from 5×1015/cm3 to 5×1016/cm3.

    Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device
    2.
    发明授权
    Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device 有权

    公开(公告)号：US11139376B2

    公开(公告)日：2021-10-05

    申请号：US16549550

    申请日：2019-08-23

    Applicant: FUJI ELECTRIC CO., LTD.

    Inventor： Akimasa Kinoshita ,  Keiji Okumura

    IPC: H01L21/02 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

    Abstract: A trench gate MOSFET has at an n-type current spreading region between an n−-type drift region and a p-type base region, a first p+-type region facing a bottom of a trench, and a second p+-type region disposed between adjacent trenches. The first and the second p+-type regions extend parallel to a first direction in which the trench extends and are partially connected by a p+-type connecting portion and thus, disposed in a ladder shape when viewed from the front surface of a semiconductor substrate. The second p+-type region has at a portion of a surface on a drain side, a recessed portion that is recessed toward a source side. One or more recessed portions is provided between connection sites in the second p+-type region for connection with the p+-type connecting portions that are adjacent to each other in the first direction X.

    Insulated gate semiconductor device with injuction supression structure and method of manufacturing same
    3.
    发明授权
    Insulated gate semiconductor device with injuction supression structure and method of manufacturing same 有权

    公开(公告)号：US10937901B2

    公开(公告)日：2021-03-02

    申请号：US16269344

    申请日：2019-02-06

    Applicant: Fuji Electric Co., Ltd.

    Inventor： Akimasa Kinoshita

    IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/16 ,  H01L29/08 ,  H01L29/10

    Abstract: Provided are: injection control regions of a second conductivity type provided on a charge transport region of a first conductivity type; main electrode regions of the first conductivity type provided on the injection control regions; insulated gate electrode structures going through the main electrode region and the injection control regions in the depth direction; an injection suppression region going through the main electrode regions and the injection control regions in the depth direction so as to form a pn junction in a path leading to the charge transport region, the injection suppression region including a semiconductor material with a narrower bandgap than a material of the charge transport region; and a contact protection region of the second conductivity type contacting the bottom surface of the injection suppression region.

    Semiconductor device
    4.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10600864B2

    公开(公告)日：2020-03-24

    申请号：US16212148

    申请日：2018-12-06

    Applicant: Fuji Electric Co., Ltd.

    Inventor： Akimasa Kinoshita ,  Keiji Okumura

    IPC: H01L29/10 ,  H01L29/78 ,  H01L29/16 ,  H01L29/06 ,  H01L21/04 ,  H01L29/66 ,  H01L21/02

    Abstract: A semiconductor device includes: a semiconductor substrate of a first conductivity type; a first semiconductor layer of the first conductivity type; a second semiconductor layer of a second conductivity type; a first semiconductor region of the first conductivity type; a trench; a second semiconductor region of the second conductivity type; a third semiconductor region of the second conductivity type; and a fourth semiconductor region of the first conductivity type. The second semiconductor region is selectively provided inside the first semiconductor layer, and the third semiconductor region is selectively provided inside the first semiconductor layer and contacts a bottom surface of the trench. The fourth semiconductor region is provided perpendicularly to a lengthwise direction of the trench in a plan view and is located at a depth position that is deeper than the second semiconductor region.

    Semiconductor device and method of manufacturing semiconductor device
    5.
    发明授权
    Semiconductor device and method of manufacturing semiconductor device 有权

    公开(公告)号：US10276653B2

    公开(公告)日：2019-04-30

    申请号：US15909977

    申请日：2018-03-01

    Applicant: FUJI ELECTRIC CO., LTD.

    Inventor： Masanobu Iwaya ,  Akimasa Kinoshita ,  Shinsuke Harada ,  Yasunori Tanaka

    IPC: H01L29/06 ,  H01L21/04 ,  H01L29/10 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

    Abstract: In a first main surface of a silicon carbide semiconductor base, a trench is formed. On a first main surface side of the silicon carbide semiconductor base, an n-type silicon carbide epitaxial layer is deposited. In a surface of the n-type silicon carbide epitaxial layer, an n-type high-concentration region is provided. In the surface of the n-type silicon carbide epitaxial layer, a first p-type base region and a second p+-type base region are selectively provided. The second p+-type base region is formed at the bottom of the trench. A depth of the n-type high-concentration region is deeper than that of the first p-type base region and the second p+-type base region. Thus, by an easy method, the electric field at a gate insulating film at the bottom of the trench is mitigated, enabling the breakdown voltage of the active region to be maintained and the ON resistance to be lowered.

    WIDE BAND GAP SEMICONDUCTOR APPARATUS AND FABRICATION METHOD THEREOF
    8.
    发明申请
    WIDE BAND GAP SEMICONDUCTOR APPARATUS AND FABRICATION METHOD THEREOF 有权
    宽带隙半导体器件及其制造方法

    公开(公告)号：US20150129894A1

    公开(公告)日：2015-05-14

    申请号：US14394045

    申请日：2013-03-14

    Applicant: FUJI ELECTRIC CO., LTD.

    Inventor： Akimasa Kinoshita ,  Takashi Tsuji ,  Kenji Fukuda

    IPC: H01L21/02 ,  H01L29/20 ,  H01L29/872 ,  H01L29/78 ,  H01L29/739 ,  H01L29/16 ,  H01L29/47

    CPC classification number: H01L27/0766 ,  H01L21/02529 ,  H01L21/0254 ,  H01L21/0495 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/47 ,  H01L29/475 ,  H01L29/6606 ,  H01L29/7393 ,  H01L29/7801 ,  H01L29/872

    Abstract: A silicon carbide epitaxial layer formed by a low concentration wide band gap semiconductor of a first conductivity type is formed on the surface of a silicon carbide substrate formed by a high concentration wide band gap semiconductor of the first conductivity type. A Schottky electrode is formed on the silicon carbide epitaxial layer. The interface between the Schottky electrode and the silicon carbide epitaxial layer is used as a Schottky interface. Plural impurity regions of a second conductivity type are disposed at predetermined intervals in a lateral direction, in the silicon carbide epitaxial layer, at a position in the lower portion of the Schottky electrode in the depth direction. Because of the shape of the impurity regions, any leak current can be suppressed without raising the ON-resistance.

    Abstract translation: 在由第一导电类型的高浓度宽带隙半导体形成的碳化硅衬底的表面上形成由第一导电类型的低浓度宽带隙半导体形成的碳化硅外延层。 在碳化硅外延层上形成肖特基电极。 肖特基电极和碳化硅外延层之间的界面用作肖特基界面。 第二导电类型的多个杂质区域在肖特基电极的深度方向的下部的位置处以碳化硅外延层的横向方向以预定间隔设置。 由于杂质区域的形状，可以抑制任何泄漏电流而不增加导通电阻。

    Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device
    9.
    发明授权
    Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device 有权

    公开(公告)号：US10418477B2

    公开(公告)日：2019-09-17

    申请号：US15800653

    申请日：2017-11-01

    Applicant: FUJI ELECTRIC CO., LTD.

    Inventor： Takeshi Tawara ,  Akimasa Kinoshita ,  Shinsuke Harada ,  Yasunori Tanaka

    IPC: H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/04

    Abstract: A silicon carbide semiconductor device, including a silicon carbide substrate, a drift layer provided on a front surface of the silicon carbide substrate, an embedded layer selectively provided in a surface layer of the drift layer, an epitaxial layer provided on the drift layer, a channel layer provided on the epitaxial layer, a source region selectively provided in a surface layer of the channel layer, a trench penetrating the source region and the channel layer and reaching the epitaxial layer, a gate electrode provided in the trench via a gate insulating film, a source electrode in contact with the channel layer and the source region, and a drain electrode provided on a rear surface of the silicon carbide substrate. The embedded layer is arranged underneath the trench in a depth direction. A longitudinal direction of the trench, which is perpendicular to the depth direction, is parallel to the off-direction of the silicon carbide substrate.

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