公开(公告)号：US20140069697A1

公开(公告)日：2014-03-13

申请号：US13990823

申请日：2011-12-02

Applicant: Jeroen Van Den Brand ,  Roel Henry Louis Kusters ,  Andreas Heinrich Dietzel

Inventor： Jeroen Van Den Brand ,  Roel Henry Louis Kusters ,  Andreas Heinrich Dietzel

IPC: H05K3/32 ,  H05K1/02

CPC classification number: H05K3/32 ,  H01L23/4985 ,  H01L24/24 ,  H01L24/76 ,  H01L24/82 ,  H01L2224/2405 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/25171 ,  H01L2224/25175 ,  H01L2224/76155 ,  H01L2224/76261 ,  H01L2224/766 ,  H01L2224/767 ,  H01L2224/82102 ,  H01L2224/82104 ,  H01L2224/82106 ,  H01L2224/82874 ,  H01L2224/9202 ,  H01L2224/92144 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0106 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K1/0283 ,  H05K1/189 ,  H05K3/12 ,  H05K3/305 ,  H05K2201/10674 ,  H05K2203/107 ,  H05K2203/1469 ,  H05K2203/1545 ,  H05K2203/175 ,  Y10T29/49133 ,  Y10T29/53178 ,  H01L2924/00

Abstract: A method is presented for assembling a component (30) with a flexible substrate (10), the component having electric contacts (31). The method comprises the steps of placing the component (30) on a first main side (11) of the substrate, applying a machine vision step to estimate a position of the electric contacts, depositing one or more layers (32) of an electrically conductive material or a precursor thereof, said layer extending over an area of the substrate defined by the component to laterally beyond said area, calculating partitioning lines depending on the estimated position of the electric contacts, partitioning the layer into mutually insulated areas (32d) by locally removing material from said layer along said partitioning lines. Also an apparatus is presented that is suitable for carrying out the method.In addition an assembly is present that can be obtained by the method and the apparatus according to the invention.

Abstract translation: 提出了一种用于将组件（30）与柔性基板（10）组装的方法，该部件具有电触点（31）。 该方法包括以下步骤：将组件（30）放置在衬底的第一主侧（11）上，施加机器视觉步骤以估计电触点的位置，沉积导电的一个或多个层（32） 材料或其前体，所述层在由所述部件限定的衬底的区域上延伸到横向超过所述区域，根据所述电触点的估计位置计算划分线，通过局部将所述层划分为相互绝缘的区域（32d） 沿着所述分隔线从所述层去除材料。 还提出了适合于执行该方法的装置。 此外，存在可以通过根据本发明的方法和装置获得的组件。

公开(公告)号：US20140048916A1

公开(公告)日：2014-02-20

申请号：US14053950

申请日：2013-10-15

Applicant: Bridge Semiconductor Corporation

Inventor： Charles W.C. LIN ,  Chia-Chung WANG

IPC: H01L23/552

CPC classification number: H01L23/552 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/24226 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8314 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2924/12042 ,  H01L2924/00

Abstract: In a preferred embodiment, a wiring board with embedded device and electromagnetic shielding includes a semiconductor device, a core layer, a shielding lid, shielding slots and build-up circuitry. The build-up circuitry covers the semiconductor device and the core layer. The shielding slots and the shielding lid are electrically connected to at least one ground contact pad of the semiconductor device by the build-up circuitry and can respectively serve as effective horizontal and vertical electromagnetic shields for the semiconductor devices.

Abstract translation: 在优选实施例中，具有嵌入式装置和电磁屏蔽的布线板包括半导体器件，芯层，屏蔽盖，屏蔽槽和积聚电路。 积聚电路覆盖半导体器件和核心层。 屏蔽槽和屏蔽盖通过积聚电路电连接到半导体器件的至少一个接地焊盘，并且可以分别用作半导体器件的有效的水平和垂直电磁屏蔽。

公开(公告)号：US08642391B2

公开(公告)日：2014-02-04

申请号：US12936765

申请日：2009-04-07

Applicant: Lea Di Cioccio ,  Francois Grossi ,  Pierric Gueguen ,  Laurent Vandroux

Inventor： Lea Di Cioccio ,  Francois Grossi ,  Pierric Gueguen ,  Laurent Vandroux

IPC: H01L21/00

CPC classification number: H01L24/83 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/82 ,  H01L24/90 ,  H01L24/95 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/08235 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/24011 ,  H01L2224/24226 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/80004 ,  H01L2224/80143 ,  H01L2224/81136 ,  H01L2224/81143 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2224/83002 ,  H01L2224/83141 ,  H01L2224/83143 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2224/95085 ,  H01L2224/95146 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/10157 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15192 ,  H01L2924/0665 ,  H01L2924/00

Abstract: A method of forming, on a surface of a substrate, at least one hydrophilic attachment area for the purpose of self-assembling a component or a chip, in which a hydrophobic area, which delimits the hydrophilic attachment area, is produced.

Abstract translation: 在衬底的表面上形成至少一个亲水附着区域的方法，用于自组装组件或芯片，其中产生界定亲水附着区域的疏水区域。

公开(公告)号：US08618654B2

公开(公告)日：2013-12-31

申请号：US13184304

申请日：2011-07-15

Applicant: Sehat Sutardja ,  Albert Wu ,  Scott Wu

Inventor： Sehat Sutardja ,  Albert Wu ,  Scott Wu

IPC: H01L23/34

CPC classification number: H01L25/50 ,  H01L23/12 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/25 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/92224 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Embodiments of the present disclosure provide a method that comprises providing a first die having a surface comprising a bond pad to route electrical signals of the first die and attaching the first die to a layer of a substrate. The method further comprises forming one or more additional layers of the substrate to embed the first die in the substrate and coupling a second die to the one or more additional layers, the second die having a surface comprising a bond pad to route electrical signals of the second die. The second die is coupled to the one or more additional layers such that electrical signals are routed between the first die and the second die.

公开(公告)号：US20130334707A1

公开(公告)日：2013-12-19

申请号：US13970053

申请日：2013-08-19

Applicant: Jiamiao Tang ,  Henry Xu ,  Shinichi Sakamoto

Inventor： Jiamiao Tang ,  Henry Xu ,  Shinichi Sakamoto

IPC: H01L25/065

CPC classification number: H01L23/49811 ,  H01L21/50 ,  H01L21/56 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5226 ,  H01L24/09 ,  H01L24/24 ,  H01L24/25 ,  H01L24/43 ,  H01L24/82 ,  H01L24/85 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L2021/60007 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/24226 ,  H01L2224/24998 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/435 ,  H01L2224/43985 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/73267 ,  H01L2224/82007 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/85138 ,  H01L2224/85815 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/48

Abstract: Some embodiments of the invention include a connecting structure between a support and at least one die attached to the support. The die includes a number of die bond pads on a surface of the die. The connecting structure includes a plurality of via and groove combinations. Conductive material is formed in the via and groove combinations to provide connection between the die bond pads and bond pads on the support. Other embodiments are described and claimed.

公开(公告)号：US20130214323A1

公开(公告)日：2013-08-22

申请号：US13816839

申请日：2011-08-12

Applicant: Karl Weidner ,  Hans Wulkesch ,  Axel Kaltenbacher ,  Walter Wegleiter ,  Johann Ramchen

Inventor： Karl Weidner ,  Hans Wulkesch ,  Axel Kaltenbacher ,  Walter Wegleiter ,  Johann Ramchen

IPC: H01L31/0232 ,  H01L33/48

CPC classification number: H01L31/0232 ,  H01L21/76804 ,  H01L24/24 ,  H01L24/82 ,  H01L33/0095 ,  H01L33/48 ,  H01L33/486 ,  H01L33/62 ,  H01L2224/18 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2933/0066 ,  H01L2224/82 ,  H01L2924/00

Abstract: A method of producing an optoelectronic semiconductor component includes providing a carrier having a top side, an underside situated opposite the top side, and a plurality of connection areas arranged at the top side alongside one another in a lateral direction; applying a plurality of optoelectronic components arranged at a distance from one another in a lateral direction at the top side, the components having a contact area facing away from the carrier; applying protective elements to the contact and connection areas; applying an electrically insulating layer to exposed locations of the carrier, contact areas and protective elements; producing openings in the insulating layer by removing protective elements; and arranging an electrically conductive material on the insulating layer and in the openings, wherein the electrically conductive material connects a contact area to an assigned connection area.

Abstract translation: 制造光电子半导体部件的方法包括提供具有顶侧，与顶侧相对设置的下侧以及沿横向彼此并排布置的多个连接区域的载体; 施加在顶侧沿横向彼此一定距离地布置的多个光电子部件，所述部件具有背离载体的接触区域; 将保护元件施加到触点和连接区域; 将电绝缘层施加到载体，接触区域和保护元件的暴露位置; 通过去除保护元件在绝缘层中产生开口; 以及在所述绝缘层和所述开口中布置导电材料，其中所述导电材料将接触区域连接到所分配的连接区域。

公开(公告)号：US20130200522A1

公开(公告)日：2013-08-08

申请号：US13836706

申请日：2013-03-15

Applicant: PANASONIC CORPORATION

Inventor： Shingo YOSHIOKA ,  Hiroaki FUJIWARA

IPC: H01L23/00

CPC classification number: H05K1/11 ,  G11B5/486 ,  H01L21/565 ,  H01L22/12 ,  H01L23/3121 ,  H01L24/03 ,  H01L24/05 ,  H01L24/24 ,  H01L24/25 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/82 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24051 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/245 ,  H01L2224/25175 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73267 ,  H01L2224/82009 ,  H01L2224/82039 ,  H01L2224/82101 ,  H01L2224/82931 ,  H01L2224/82947 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2224/92244 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K1/111 ,  H05K1/117 ,  H05K1/181 ,  H05K3/184 ,  H05K2201/0376 ,  H05K2201/09472 ,  Y02P70/611 ,  Y10T428/1171 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of mounting a semiconductor chip includes: forming a resin coating on a surface of a path connecting a bonding pad on a surface of a semiconductor chip and an electrode pad formed on a surface of an insulating base material; forming, by laser beam machining, a wiring gutter having a depth that is equal to or greater than a thickness of the resin coating along the path for connecting the bonding pad and the electrode pad; depositing a plating catalyst on a surface of the wiring gutter; removing the resin coating; and forming an electroless plating coating only at a site where the plating catalyst remains.

Abstract translation: 安装半导体芯片的方法包括：在连接半导体芯片的表面上的接合焊盘和形成在绝缘基材的表面上的电极焊盘的路径的表面上形成树脂涂层; 通过激光束加工形成具有等于或大于沿着用于连接焊盘和电极焊盘的路径的树脂涂层的厚度的深度的布线槽; 在布线槽的表面上沉积电镀催化剂; 去除树脂涂层; 并且仅在电镀催化剂保留的部位形成化学镀层。

公开(公告)号：US08482137B2

公开(公告)日：2013-07-09

申请号：US13144112

申请日：2010-01-26

Applicant: Shingo Yoshioka ,  Hiroaki Fujiwara

Inventor： Shingo Yoshioka ,  Hiroaki Fujiwara

IPC: H01L23/48

CPC classification number: H05K1/11 ,  G11B5/486 ,  H01L21/565 ,  H01L22/12 ,  H01L23/3121 ,  H01L24/03 ,  H01L24/05 ,  H01L24/24 ,  H01L24/25 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/82 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24051 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/245 ,  H01L2224/25175 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73267 ,  H01L2224/82009 ,  H01L2224/82039 ,  H01L2224/82101 ,  H01L2224/82931 ,  H01L2224/82947 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2224/92244 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K1/111 ,  H05K1/117 ,  H05K1/181 ,  H05K3/184 ,  H05K2201/0376 ,  H05K2201/09472 ,  Y02P70/611 ,  Y10T428/1171 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: One aspect of the present invention is a method of mounting a semiconductor chip having: a step of forming a resin coating on a surface of a path connecting a bonding pad on a surface of a semiconductor chip and an electrode pad formed on a surface of an insulating base material; a step of forming, by laser beam machining, a wiring gutter having a depth that is equal to or greater than a thickness of the resin coating along the path for connecting the bonding pad and the electrode pad; a step of depositing a plating catalyst on a surface of the wiring gutter; a step of removing the resin coating; and a step of forming an electroless plating coating only at a site where the plating catalyst remains. Another aspect of the present invention is a three-dimensional structure in which a wiring is formed on a surface, wherein, on the surface of the three-dimensional structure, a recessed gutter for wiring is formed, extending between mutually intersecting adjacent faces of the three-dimensional structure, and wherein at least a part of a wiring conductor is embedded in the recessed gutter for wiring.

Abstract translation: 本发明的一个方面是一种安装半导体芯片的方法，该半导体芯片具有：在连接半导体芯片的表面上的接合焊盘的表面上形成树脂涂层的步骤和形成在半导体芯片的表面上的电极焊盘 绝缘基材; 通过激光束加工形成具有等于或大于沿着用于连接焊盘和电极焊盘的路径的树脂涂层的厚度的深度的布线槽的步骤; 将电镀催化剂沉积在布线槽的表面上的步骤; 去除树脂涂层的步骤; 以及仅在电镀催化剂保留的部位形成化学镀镀层的工序。 本发明的另一方面是其中在表面上形成布线的三维结构，其中在三维结构的表面上形成用于布线的凹槽，在相互相交的相邻面之间延伸 三维结构，并且其中布线导体的至少一部分嵌入到凹槽中用于布线。

公开(公告)号：US08461696B2

公开(公告)日：2013-06-11

申请号：US12647953

申请日：2009-12-28

Applicant: Kyu Won Lee ,  Qwan Ho Chung

Inventor： Kyu Won Lee ,  Qwan Ho Chung

IPC: H01L23/12 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L24/27 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/28 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/24225 ,  H01L2224/24226 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2225/1058 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/078 ,  H01L2924/07802 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/3512

Abstract: A substrate for a semiconductor package is provided having first and second core layers defining a cavity having an adhesive member and sized and shaped to receive a semiconductor chip. The semiconductor package further having a connection member formed on a bond finger and connected to a via pattern formed through the first and second core layers. A stack package is also provided having multiple substrates.

Abstract translation: 提供了一种用于半导体封装的衬底，其具有限定具有粘合构件的空腔的第一和第二芯层，并且其尺寸和形状用于容纳半导体芯片。 所述半导体封装还具有连接构件，所述连接构件形成在接合指状物上并且连接到通过所述第一和第二芯层形成的通孔图案。 还提供具有多个基板的堆叠封装。

公开(公告)号：US08441804B2

公开(公告)日：2013-05-14

申请号：US12179912

申请日：2008-07-25

Applicant: Oliver Haeberlen ,  Klaus Schiess ,  Stefan Kramp

Inventor： Oliver Haeberlen ,  Klaus Schiess ,  Stefan Kramp

IPC: H05K7/00

CPC classification number: H01L21/50 ,  H01L21/561 ,  H01L23/142 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/492 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H01L24/97 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05572 ,  H01L2224/05639 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/13099 ,  H01L2224/24226 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2224/19 ,  H01L2924/00 ,  H01L2224/05099

Abstract: A semiconductor device and method of manufacturing a semiconductor device. One embodiment provides an electrically conductive carrier. A semiconductor chip is placed over the carrier. An electrically insulating layer is applied over the carrier and the semiconductor chip. The electrically insulating layer has a first face facing the carrier and a second face opposite to the first face. A first through-hole is in the electrically insulating layer. Solder material is deposited in the first through-hole and on the second face of the electrically insulating layer.

Abstract translation: 半导体器件及半导体器件的制造方法。 一个实施例提供导电载体。 半导体芯片放置在载体上。 在载体和半导体芯片上施加电绝缘层。 电绝缘层具有面向载体的第一面和与第一面相对的第二面。 第一通孔位于电绝缘层中。 焊料沉积在电绝缘层的第一通孔和第二面上。