公开(公告)号：US20160380183A1

公开(公告)日：2016-12-29

申请号：US15000289

申请日：2016-01-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Chem-Yow Hsu ,  Shih-Chang Liu

IPC: H01L43/04 ,  H01L43/08 ,  H01L43/12

CPC classification number: H01L43/08 ,  H01L27/228 ,  H01L43/12

Abstract: Some embodiments relate to an integrated circuit including a magnetoresistive random-access memory (MRAM) cell. The integrated circuit includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a plurality of dielectric layers and a plurality of metal layers that are stacked over one another in alternating fashion. The plurality of metal layers include a lower metal layer and an upper metal layer disposed over the lower metal layer. A bottom electrode is disposed over and in electrical contact with the lower metal layer. A magnetic tunneling junction (MTJ) is disposed over an upper surface of bottom electrode. A top electrode is disposed over an upper surface of the MTJ and is in direct electrical contact with a lower surface of the upper metal layer.

Abstract translation: 一些实施例涉及包括磁阻随机存取存储器（MRAM）单元的集成电路。 集成电路包括设置在半导体衬底上的半导体衬底和互连结构。 互连结构包括以交替方式彼此叠置的多个电介质层和多个金属层。 多个金属层包括下金属层和设置在下金属层上的上金属层。 底部电极设置在下部金属层的上方并与之接触。 磁性隧道结（MTJ）设置在底部电极的上表面上。 顶部电极设置在MTJ的上表面上方并与上金属层的下表面直接电接触。

公开(公告)号：US09502533B2

公开(公告)日：2016-11-22

申请号：US14835958

申请日：2015-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Wei Cheng Wu ,  Kong-Pin Chang ,  Chia Ming Liang ,  Meng-Fang Hsu ,  Ching-Feng Fu ,  Shih-Ting Hung

IPC: H01L21/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7851

Abstract: Some embodiments of the present disclosure relate to a method. In this method, a semiconductor substrate, which has an active region disposed in the semiconductor substrate, is received. A shallow trench isolation (STI) structure is formed to laterally surround the active region. An upper surface of the active region bounded by the STI structure is recessed to below an upper surface of the STI structure. The recessed upper surface extends continuously between inner sidewalls of the STI structure and leaves upper portions of the inner sidewalls of the STI structure exposed. A semiconductor layer is epitaxially grown on the recessed surface of the active region between the inner sidewalls of the STI structure. A gate dielectric is formed over the epitaxially-grown semiconductor layer. A conductive gate electrode is formed over the gate dielectric.

Abstract translation: 本公开的一些实施例涉及一种方法。 在该方法中，接收具有设置在半导体衬底中的有源区的半导体衬底。 形成浅沟槽隔离（STI）结构以横向围绕有源区域。 由STI结构限定的有源区的上表面凹入到STI结构的上表面的下方。 凹陷的上表面在STI结构的内侧壁之间连续延伸，并且使STI结构的内侧壁的上部露出。 在STI结构的内侧壁之间的有源区的凹面上外延生长半导体层。 在外延生长的半导体层上形成栅极电介质。 在栅极电介质上形成导电栅电极。

公开(公告)号：US09425206B2

公开(公告)日：2016-08-23

申请号：US14580454

申请日：2014-12-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Fang-Lan Chu

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L27/115

CPC classification number: H01L27/11573 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11548 ,  H01L27/11575 ,  H01L29/517 ,  H01L29/66545

Abstract: The present disclosure relates to a structure and method for reducing CMP dishing in integrated circuits. In some embodiments, the structure has a semiconductor substrate with an embedded memory region and a periphery region. one or more dummy structures are formed between the memory region and the periphery region. Placement of the dummy structures between the embedded memory region and the periphery region causes the surface of a deposition layer therebetween to become more planar after being polished without resulting in a dishing effect. The reduced recess reduces metal residue formation and thus leakage and shorting of current due to metal residue. Further, less dishing will reduce the polysilicon loss of active devices. In some embodiments, one of the dummy structures is formed with an angled sidewall which eliminates the need for a boundary cut etch process.

Abstract translation: 本公开涉及用于减少集成电路中的CMP凹陷的结构和方法。 在一些实施例中，该结构具有具有嵌入的存储区域和外围区域的半导体衬底。 在存储区域和外围区域之间形成一个或多个虚拟结构。 在嵌入的存储区域和外围区域之间的虚拟结构的放置使得其之间的沉积层的表面在抛光之后变得更平坦，而不会产生凹陷效应。 减少的凹陷减少金属残留物的形成，从而导致金属残留物导致的电流泄漏和短路。 此外，较少的凹陷将减少有源器件的多晶硅损耗。 在一些实施例中，虚拟结构之一形成有成角度的侧壁，其消除了对边界切割蚀刻工艺的需要。

公开(公告)号：US20160233228A1

公开(公告)日：2016-08-11

申请号：US14645993

申请日：2015-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Chien-Hung Chang

IPC: H01L27/115 ,  H01L29/51 ,  H01L21/28 ,  H01L49/02

CPC classification number: H01L21/28273 ,  H01L27/11524 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11541 ,  H01L27/11543 ,  H01L29/42328 ,  H01L29/42332

Abstract: The present disclosure relates to a non-planar FEOL (front-end-of-the-line) capacitor comprising a charge trapping dielectric layer disposed between electrodes, and an associated method of fabrication. In some embodiments, the non-planar FEOL capacitor has a first electrode disposed over a substrate. A charge trapping dielectric layer is disposed onto the substrate at a position adjacent to the first electrode. The charge trapping dielectric layer has an “L” shape, with a lateral component extending in a first direction and a vertical component extending in a second direction. A second electrode is arranged onto the lateral component and is separated from the first electrode by the first component.

Abstract translation: 本公开涉及一种包括设置在电极之间的电荷捕获介电层的非平面FEOL（前端线）电容器和相关的制造方法。 在一些实施例中，非平面FEOL电容器具有设置在衬底上的第一电极。 电荷捕获电介质层在与第一电极相邻的位置处设置在基板上。 电荷俘获介电层具有“L”形状，其中侧向分量沿第一方向延伸，垂直分量沿第二方向延伸。 第二电极布置在侧向部件上并且通过第一部件与第一电极分离。

公开(公告)号：US20160190143A1

公开(公告)日：2016-06-30

申请号：US14851284

申请日：2015-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Yu-Hsiung Wang ,  Chen-Chin Liu

IPC: H01L27/115 ,  H01L29/40 ,  H01L21/28 ,  H01L29/792 ,  H01L29/66 ,  H01L27/07 ,  H01L29/423

CPC classification number: H01L29/42344 ,  H01L27/0629 ,  H01L27/11573 ,  H01L28/90 ,  H01L29/408

Abstract: Some embodiments relate to an integrated circuit (IC). The IC includes a semiconductor substrate including a flash memory region and a capacitor region. A flash memory cell is arranged over the flash memory region and includes a polysilicon select gate arranged between first and second source/drain regions of the flash memory cell. The flash memory cell also includes a control gate arranged alongside the select gate and separated from the select gate by a control gate dielectric layer. A capacitor is arranged over the capacitor region and includes: a polysilicon first capacitor plate and polysilicon second capacitor plate, which are inter-digitated with one another and separated from one another by a capacitor dielectric layer. The capacitor dielectric layer and control gate dielectric layer are made of the same material.

Abstract translation: 一些实施例涉及集成电路（IC）。 IC包括包括闪存区域和电容器区域的半导体衬底。 闪存单元布置在闪速存储器区域上，并且包括布置在闪存单元的第一和第二源/漏区之间的多晶硅选择栅极。 闪速存储器单元还包括一个控制栅极，该控制栅极与选择栅极并排设置，并通过控制栅极电介质层与选择栅极分离。 电容器布置在电容器区域上，包括：多晶硅第一电容器板和多晶硅第二电容器板，它们彼此互数位化并且通过电容器介电层彼此分离。 电容介质层和控制栅介质层由相同的材料制成。

公开(公告)号：US20160141298A1

公开(公告)日：2016-05-19

申请号：US14547251

申请日：2014-11-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Ya-Chen Kao

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/06

CPC classification number: H01L27/11563 ,  H01L21/28008 ,  H01L21/76229 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/0653 ,  H01L29/4234 ,  H01L29/66545

Abstract: The present disclosure relates to a structure and method for reducing contact over-etching and high contact resistance (Rc) on an embedded flash memory HKMG integrated circuit. In one embodiment, an STI region underlying a memory contact pad region is recessed to make the STI surface substantially co-planar with the rest of the semiconductor substrate. The recess allows formation of thicker memory contact pad structures. The thicker polysilicon on these contact pad structures prevents contact over-etching and thus reduces the Rc of contacts formed thereon.

Abstract translation: 本发明涉及用于在嵌入式闪速存储器HKMG集成电路上减少接触过蚀刻和高接触电阻（Rc）的结构和方法。 在一个实施例中，存储器接触焊盘区域下面的STI区域是凹进的，以使STI表面与半导体衬底的其余部分基本上共面。 该凹槽允许形成更厚的记忆接触垫结构。 这些接触焊盘结构上较厚的多晶硅防止接触过蚀刻，从而减少形成在其上的触点的Rc。

公开(公告)号：US20150263010A1

公开(公告)日：2015-09-17

申请号：US14210796

申请日：2014-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Chin-Yi Huang ,  Shih-Chang Liu ,  Chang-Ming Wu

IPC: H01L27/11 ,  H01L27/115

CPC classification number: H01L27/11534 ,  H01L27/11521 ,  H01L29/66545

Abstract: The present disclosure relates to a method of embedding an ESF3 memory in a HKMG integrated circuit that utilizes a replacement gate technology. The ESF3 memory is formed over a recessed substrate which prevents damage of the memory control gates during the CMP process performed on the ILD layer. An asymmetric isolation zone is also formed in the transition region between the memory cell and the periphery circuit boundary.

Abstract translation: 本公开涉及一种在采用替代门技术的HKMG集成电路中嵌入ESF3存储器的方法。 ESF3存储器形成在凹陷的衬底上，防止在ILD层执行的CMP工艺期间对存储器控制栅极的损坏。 在存储单元和外围电路边界之间的过渡区域中也形成非对称隔离区。

公开(公告)号：US11903191B2

公开(公告)日：2024-02-13

申请号：US17231204

申请日：2021-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Harry-Hak-Lay Chuang

IPC: H10B41/30 ,  H01L21/28 ,  H01L27/105 ,  H01L21/8234 ,  H01L29/66 ,  H10B41/49 ,  H10B43/00 ,  H10B43/30 ,  H01L21/306 ,  H01L21/321 ,  H10B10/00

CPC classification number: H10B41/30 ,  H01L21/30604 ,  H01L21/3212 ,  H01L21/823462 ,  H01L27/105 ,  H01L29/40114 ,  H01L29/66545 ,  H10B41/49 ,  H10B43/00 ,  H10B43/30 ,  H10B10/18

Abstract: An embedded flash memory device includes a gate stack, which includes a bottom dielectric layer extending into a recess in a semiconductor substrate, and a charge storage layer over the bottom dielectric layer. The charge storage layer includes a portion in the recess. The gate stack further includes a top dielectric layer over the charge storage layer, and a metal gate over the top dielectric layer. Source and drain regions are in the semiconductor substrate, and are on opposite sides of the gate stack.

公开(公告)号：US11653572B2

公开(公告)日：2023-05-16

申请号：US17184997

申请日：2021-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Tien-Wei Chiang ,  Wen-Chun You

IPC: H01L29/82 ,  H01L43/12 ,  H01L27/22 ,  H01L43/08

CPC classification number: H01L43/12 ,  H01L27/228 ,  H01L43/08

Abstract: Some embodiments relate to a magnetoresistive random-access memory (MRAM) cell. The cell includes a bottom electrode having a central bottom electrode portion surrounded by a peripheral bottom electrode portion. Step regions of the conductive bottom electrode couple the central and peripheral bottom electrode portions to one another such that an upper surface of the central portion is recessed relative to an upper surface of the peripheral portion. A magnetic tunneling junction (MTJ) has MTJ outer sidewalls which are disposed over the bottom central electrode portion and which are arranged between the step regions. A top electrode is disposed over an upper surface of the MTJ. Other devices and methods are also disclosed.

公开(公告)号：US11489107B2

公开(公告)日：2022-11-01

申请号：US17009905

申请日：2020-09-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Che Ku ,  Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Tsun Chung Tu ,  Jiunyu Tsai ,  Sheng-Huang Huang

IPC: H01L43/02 ,  H01F10/32 ,  H01L27/22 ,  H01L43/12 ,  H01L23/528 ,  H01L21/768 ,  H01F41/34 ,  H01L23/522 ,  G11C11/16

Abstract: The present disclosure relates to a method of forming an integrated chip. The method includes forming an ILD layer over a memory device over a substrate. A hard mask structure is formed over the ILD layer and a patterning structure is formed over the hard mask structure. The hard mask structure has sidewalls defining a first opening directly over the memory device and centered along a first line perpendicular to an upper surface of the substrate. The patterning structure has sidewalls defining a second opening directly over the memory device and centered along a second line parallel to the first line. The second line is laterally offset from the first line by a non-zero distance. The ILD layer is etched below an overlap of the first and second openings to define a top electrode via hole. The top electrode via hole is with a conductive material.