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    BOUNDARY SCHEME FOR EMBEDDED POLY-SiON CMOS OR NVM IN HKMG CMOS TECHNOLOGY
    2.
    发明申请
    BOUNDARY SCHEME FOR EMBEDDED POLY-SiON CMOS OR NVM IN HKMG CMOS TECHNOLOGY 有权
    嵌入式POLY-SiON CMOS或NVM的HKMG CMOS技术的边界方案

    公开(公告)号：US20160181268A1

    公开(公告)日：2016-06-23

    申请号：US14580454

    申请日：2014-12-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Fang-Lan Chu

    IPC: H01L27/115

    CPC classification number: H01L27/11573 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11548 ,  H01L27/11575 ,  H01L29/517 ,  H01L29/66545

    Abstract: The present disclosure relates to a structure and method for reducing CMP dishing in integrated circuits. In some embodiments, the structure has a semiconductor substrate with an embedded memory region and a periphery region. one or more dummy structures are formed between the memory region and the periphery region. Placement of the dummy structures between the embedded memory region and the periphery region causes the surface of a deposition layer therebetween to become more planar after being polished without resulting in a dishing effect. The reduced recess reduces metal residue formation and thus leakage and shorting of current due to metal residue. Further, less dishing will reduce the polysilicon loss of active devices. In some embodiments, one of the dummy structures is formed with an angled sidewall which eliminates the need for a boundary cut etch process.

    Abstract translation: 本公开涉及用于减少集成电路中的CMP凹陷的结构和方法。 在一些实施例中，该结构具有具有嵌入的存储区域和外围区域的半导体衬底。 在存储区域和外围区域之间形成一个或多个虚拟结构。 在嵌入的存储区域和外围区域之间的虚拟结构的放置使得其之间的沉积层的表面在抛光之后变得更平坦，而不会产生凹陷效应。 减少的凹陷减少金属残留物的形成，从而导致金属残留物导致的电流泄漏和短路。 此外，较少的凹陷将减少有源器件的多晶硅损耗。 在一些实施例中，虚拟结构之一形成有成角度的侧壁，其消除了对边界切割蚀刻工艺的需要。

    Boundary scheme for embedded poly-SiON CMOS or NVM in HKMG CMOS technology
    4.
    发明授权
    Boundary scheme for embedded poly-SiON CMOS or NVM in HKMG CMOS technology 有权
    HKMG CMOS技术中嵌入式多晶硅CMOS或NVM的边界方案

    公开(公告)号：US09425206B2

    公开(公告)日：2016-08-23

    申请号：US14580454

    申请日：2014-12-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Fang-Lan Chu

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L27/115

    CPC classification number: H01L27/11573 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11548 ,  H01L27/11575 ,  H01L29/517 ,  H01L29/66545

    Abstract: The present disclosure relates to a structure and method for reducing CMP dishing in integrated circuits. In some embodiments, the structure has a semiconductor substrate with an embedded memory region and a periphery region. one or more dummy structures are formed between the memory region and the periphery region. Placement of the dummy structures between the embedded memory region and the periphery region causes the surface of a deposition layer therebetween to become more planar after being polished without resulting in a dishing effect. The reduced recess reduces metal residue formation and thus leakage and shorting of current due to metal residue. Further, less dishing will reduce the polysilicon loss of active devices. In some embodiments, one of the dummy structures is formed with an angled sidewall which eliminates the need for a boundary cut etch process.

    Abstract translation: 本公开涉及用于减少集成电路中的CMP凹陷的结构和方法。 在一些实施例中，该结构具有具有嵌入的存储区域和外围区域的半导体衬底。 在存储区域和外围区域之间形成一个或多个虚拟结构。 在嵌入的存储区域和外围区域之间的虚拟结构的放置使得其之间的沉积层的表面在抛光之后变得更平坦，而不会产生凹陷效应。 减少的凹陷减少金属残留物的形成，从而导致金属残留物导致的电流泄漏和短路。 此外，较少的凹陷将减少有源器件的多晶硅损耗。 在一些实施例中，虚拟结构之一形成有成角度的侧壁，其消除了对边界切割蚀刻工艺的需要。

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