公开(公告)号：US11063058B2

公开(公告)日：2021-07-13

申请号：US16875934

申请日：2020-05-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Harry-Hak-Lay Chuang ,  Wei-Cheng Wu ,  Ya-Chen Kao

IPC: H01L27/11568 ,  H01L29/66 ,  H01L27/11573 ,  H01L29/423 ,  H01L29/51 ,  H01L21/8238

Abstract: A memory device includes a semiconductor substrate, a select gate stack, a main gate, a charge trapping layer, and a spacer. The a select gate stack is over the semiconductor substrate. The main gate is over the semiconductor substrate. The charge trapping layer has a first portion between the main gate and the semiconductor substrate. The spacer is on a sidewall of the main gate. At least a portion of the main gate is between the spacer and the select gate stack, and a lowermost surface of the spacer is above a lowermost surface of the main gate.

公开(公告)号：US20190252400A1

公开(公告)日：2019-08-15

申请号：US16396937

申请日：2019-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Ya-Chen Kao ,  Yi Hsien Lu

IPC: H01L27/11573 ,  H01L29/66 ,  H01L27/092 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/51

CPC classification number: H01L27/11573 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/092 ,  H01L29/42344 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656

Abstract: The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-κ metal gate) integrated circuit which includes a high-voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size.

公开(公告)号：US10050050B2

公开(公告)日：2018-08-14

申请号：US14075817

申请日：2013-11-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Harry Hak-Lay Chuang ,  Wei-Cheng Wu ,  Ya-Chen Kao

IPC: H01L29/792 ,  H01L27/11568 ,  H01L29/66 ,  H01L27/11573 ,  H01L29/423 ,  H01L29/51 ,  H01L21/8238

Abstract: A semiconductor device includes a substrate, at least one split gate memory device, and at least one logic device. The split gate memory device is disposed on the substrate. The logic device is disposed on the substrate. A select gate or a main gate of the split gate memory device and a logic gate of the logic device are both made of metal, and the other gate of the split gate memory device is made of nonmetal.

公开(公告)号：US20170236833A1

公开(公告)日：2017-08-17

申请号：US15582889

申请日：2017-05-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Ya-Chen Kao ,  Yi Hsien Lu

IPC: H01L27/11573 ,  H01L29/66 ,  H01L29/423 ,  H01L29/51 ,  H01L21/8234 ,  H01L27/092

CPC classification number: H01L27/11573 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/092 ,  H01L29/42344 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656

Abstract: The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-κ metal gate) integrated circuit which includes a high-voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size.

公开(公告)号：US09431413B2

公开(公告)日：2016-08-30

申请号：US14547251

申请日：2014-11-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Ya-Chen Kao

IPC: H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L27/115 ,  H01L29/06 ,  H01L21/28

CPC classification number: H01L27/11563 ,  H01L21/28008 ,  H01L21/76229 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/0653 ,  H01L29/4234 ,  H01L29/66545

Abstract: The present disclosure relates to a structure and method for reducing contact over-etching and high contact resistance (Rc) on an embedded flash memory HKMG integrated circuit. In one embodiment, an STI region underlying a memory contact pad region is recessed to make the STI surface substantially co-planar with the rest of the semiconductor substrate. The recess allows formation of thicker memory contact pad structures. The thicker polysilicon on these contact pad structures prevents contact over-etching and thus reduces the Rc of contacts formed thereon.

Abstract translation: 本发明涉及用于在嵌入式闪存HKMG集成电路上减少接触过蚀刻和高接触电阻（Rc）的结构和方法。 在一个实施例中，存储器接触焊盘区域下面的STI区域是凹进的，以使STI表面与半导体衬底的其余部分基本上共面。 该凹槽允许形成更厚的记忆接触垫结构。 这些接触焊盘结构上较厚的多晶硅防止接触过蚀刻，从而减少形成在其上的触点的Rc。

公开(公告)号：US20160225776A1

公开(公告)日：2016-08-04

申请号：US14609575

申请日：2015-01-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Chin-Yi Huang ,  Ya-Chen Kao

IPC: H01L27/115 ,  H01L21/3213 ,  H01L21/321 ,  H01L21/762 ,  H01L29/06 ,  H01L21/28

CPC classification number: H01L27/11507 ,  H01L21/28273 ,  H01L21/32115 ,  H01L21/3212 ,  H01L21/32139 ,  H01L21/76229 ,  H01L27/11521 ,  H01L29/0649 ,  H01L29/66825

Abstract: The present disclosure relates an integrated circuit (IC) for an embedded flash memory device. In some embodiments, the IC includes a memory array region and a boundary region surrounding the memory array region disposed over a semiconductor substrate. A hard mask is disposed at the memory array region comprising a plurality of discrete portions. The hard mask is disposed under a control dielectric layer of the memory array region.

Abstract translation: 本公开涉及用于嵌入式闪存器件的集成电路（IC）。 在一些实施例中，IC包括存储器阵列区域和围绕设置在半导体衬底上的存储器阵列区域的边界区域。 在包括多个离散部分的存储器阵列区域处设置硬掩模。 硬掩模设置在存储器阵列区域的控制介质层的下方。

公开(公告)号：US09202817B2

公开(公告)日：2015-12-01

申请号：US14161372

申请日：2014-01-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Harry Hak-Lay Chuang ,  Wei-Cheng Wu ,  Ya-Chen Kao

IPC: H01L21/336 ,  H01L27/115 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L27/1157 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/42332 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device includes a substrate, at least one split gate memory device, and at least one logic device. The split gate memory device is disposed on the substrate. The logic device is disposed on the substrate. At least one of a select gate and a main gate of the split gate memory device and a logic gate of the logic device are made of metal. The method for manufacturing the semiconductor device includes forming at least one split gate stack and at least one logic gate stack and respectively replacing at least one of a dummy gate layer and a main gate layer in the split gate stack and the dummy gate layer in the logic gate stack with at least one metal memory gate and a metal logic gate.

Abstract translation: 本发明提供一种半导体器件及其制造方法。 半导体器件包括衬底，至少一个分离栅极存储器件和至少一个逻辑器件。 分离栅极存储器件设置在衬底上。 逻辑器件设置在衬底上。 分离栅极存储器件的选择栅极和主栅极中的至少一个以及逻辑器件的逻辑门由金属制成。 半导体器件的制造方法包括形成至少一个分离栅极堆叠和至少一个逻辑门极堆叠，并且分别替代分离栅极堆叠中的伪栅极层和主栅极层中的至少一个以及虚拟栅极层中的至少一个 具有至少一个金属存储器栅极和金属逻辑门的逻辑门极堆叠。

公开(公告)号：US11672124B2

公开(公告)日：2023-06-06

申请号：US17184953

申请日：2021-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Ya-Chen Kao ,  Yi Hsien Lu

IPC: H10B43/40 ,  H01L29/66 ,  H01L29/423 ,  H01L29/51 ,  H01L27/11573 ,  H01L21/8234 ,  H01L27/092 ,  H01L27/088

CPC classification number: H01L27/11573 ,  H01L21/823462 ,  H01L27/092 ,  H01L29/42344 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66545 ,  H01L27/088

Abstract: The present disclosure relates to an integrated circuit that includes a semiconductor substrate having a periphery region and memory cell region separated by a boundary region. A pair of split gate flash memory cells are disposed on the memory cell region and include a first select gate and a first memory gate. A first gate electrode is disposed over a first gate dielectric layer on the periphery region. A second gate electrode is disposed over a second gate dielectric layer on the periphery region at a position between the boundary region and the first gate electrode. The second dielectric layer is thicker than the first gate dielectric layer. The first select gate and the first memory gate have upper surfaces that are co-planar or level with the upper surface of the second gate electrode.

公开(公告)号：US11088040B2

公开(公告)日：2021-08-10

申请号：US16578303

申请日：2019-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Ya-Chen Kao ,  Chen-Chin Liu ,  Chih-Pin Huang

IPC: H01L21/66 ,  H01L27/11529 ,  H01L27/11524 ,  H01L27/11526 ,  H01L29/423 ,  H01L27/11519

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.

公开(公告)号：US20200083126A1

公开(公告)日：2020-03-12

申请号：US16682210

申请日：2019-11-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Ya-Chen Kao ,  Chen-Chin Liu ,  Chih-Pin Huang

IPC: H01L21/66 ,  H01L27/11529 ,  H01L27/11524 ,  H01L27/11526 ,  H01L29/423

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.