公开(公告)号：US20210066323A1

公开(公告)日：2021-03-04

申请号：US16800167

申请日：2020-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yong-Sheng Huang ,  Ming Chyi Liu ,  Chih-Pin Huang

IPC: H01L27/11521 ,  H01L23/528 ,  H01L23/522 ,  H01L29/788 ,  H01L21/768 ,  H01L21/311 ,  H01L21/762 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66

Abstract: Various embodiments of the present disclosure are directed towards a method for opening a source line in a memory device. An erase gate line (EGL) and the source line are formed elongated in parallel. The source line underlies the EGL and is separated from the EGL by a dielectric layer. A first etch is performed to form a first opening through the EGL and stops on the dielectric layer. A second etch is performed to thin the dielectric layer at the first opening, wherein the first and second etches are performed with a common mask in place. A silicide process is performed to form a silicide layer on the source line at the first opening, wherein the silicide process comprises a third etch with a second mask in place and extends the first opening through the dielectric layer. A via is formed extending through the EGL to the silicide layer.

公开(公告)号：US20200058665A1

公开(公告)日：2020-02-20

申请号：US16574220

申请日：2019-09-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Wei Cheng Wu ,  Chih-Pin Huang

IPC: H01L27/11548 ,  H01L29/423 ,  H01L21/768 ,  H01L29/66 ,  H01L21/321 ,  H01L21/033 ,  H01L23/532 ,  H01L27/11524 ,  H01L21/762

Abstract: Various embodiments of the present application are directed to an embedded memory boundary structure with a boundary sidewall spacer, and associated forming methods. In some embodiments, an isolation structure is disposed in a semiconductor substrate to separate a memory region from a logic region. A memory cell structure is disposed on the memory region and a cell boundary structure is formed on the isolation structure including a boundary sidewall spacer. A protecting dielectric layer is disposed on a top surface of the boundary sidewall spacer. The boundary sidewall spacer and the protecting dielectric layer provide a smooth boundary sidewall that is not subject to damage during formation of the logic device structure and, hence, is not subject to trapping high κ etch residue during formation of the logic device structure with HKMG technology.

公开(公告)号：US11264292B2

公开(公告)日：2022-03-01

申请号：US16682210

申请日：2019-11-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Ya-Chen Kao ,  Chen-Chin Liu ,  Chih-Pin Huang

IPC: H01L27/11529 ,  H01L27/11524 ,  H01L27/11526 ,  H01L29/423 ,  H01L27/11519 ,  H01L21/66

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.

公开(公告)号：US20200105777A1

公开(公告)日：2020-04-02

申请号：US16169156

申请日：2018-10-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Chen-Chin Liu ,  Chih-Pin Huang

IPC: H01L27/11548 ,  H01L27/11519 ,  H01L27/11529 ,  H01L29/423 ,  H01L29/51 ,  H01L21/308 ,  H01L21/033 ,  H01L21/321 ,  H01L21/28

Abstract: Some embodiments of the present application are directed towards an integrated circuit (IC). The integrated circuit includes a semiconductor substrate having a peripheral region and a memory cell region separated by an isolation structure. The isolation structure extends into a top surface of the semiconductor substrate and comprises dielectric material. A logic device is arranged on the peripheral region. A memory device is arranged on the memory region. The memory device includes a gate electrode and a memory hardmask over the gate electrode. An anti-dishing structure is disposed on the isolation structure. An upper surface of the anti-dishing structure and an upper surface of the memory hardmask have equal heights as measured from the top surface of the semiconductor substrate.

公开(公告)号：US10535574B2

公开(公告)日：2020-01-14

申请号：US15962177

申请日：2018-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Ya-Chen Kao ,  Chen-Chin Liu ,  Chih-Pin Huang

IPC: H01L21/66 ,  H01L27/11529 ,  H01L27/11524 ,  H01L27/11519

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.

公开(公告)号：US11854823B2

公开(公告)日：2023-12-26

申请号：US17574414

申请日：2022-01-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Chih-Pin Huang ,  Ching-Wen Chan

IPC: H01L21/3105 ,  H01L21/308 ,  H01L21/762 ,  H10B41/30

CPC classification number: H01L21/31056 ,  H01L21/3086 ,  H01L21/76283 ,  H10B41/30

Abstract: An integrated circuit device includes a substrate, a first isolation feature, a memory cell, and a semiconductor device. The substrate has a cell region, a peripheral region, and a transition region between the cell region and the peripheral region. The first isolation feature is in the transition region. The substrate includes a protrusion portion between a first portion and a second portion of the first isolation feature, the second portion is between the first portion and the cell region, and a top surface of the first portion of the first isolation feature has a first part and a second part lower than the first part, and the second part is between the first part and the second portion of the first isolation feature. The memory cell is over the cell region of the substrate. The semiconductor device is over the peripheral region of the substrate.

公开(公告)号：US11031409B2

公开(公告)日：2021-06-08

申请号：US16574220

申请日：2019-09-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Wei Cheng Wu ,  Chih-Pin Huang

IPC: H01L27/11548 ,  H01L29/423 ,  H01L29/66 ,  H01L23/532 ,  H01L27/11524 ,  H01L21/768 ,  H01L21/033 ,  H01L21/762 ,  H01L21/321

Abstract: Various embodiments of the present application are directed to an embedded memory boundary structure with a boundary sidewall spacer, and associated forming methods. In some embodiments, an isolation structure is disposed in a semiconductor substrate to separate a memory region from a logic region. A memory cell structure is disposed on the memory region and a cell boundary structure is formed on the isolation structure including a boundary sidewall spacer. A protecting dielectric layer is disposed on a top surface of the boundary sidewall spacer. The boundary sidewall spacer and the protecting dielectric layer provide a smooth boundary sidewall that is not subject to damage during formation of the logic device structure and, hence, is not subject to trapping high κ etch residue during formation of the logic device structure with HKMG technology.

公开(公告)号：US10804281B2

公开(公告)日：2020-10-13

申请号：US16169156

申请日：2018-10-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Chen-Chin Liu ,  Chih-Pin Huang

IPC: H01L29/78 ,  H01L27/11548 ,  H01L27/11519 ,  H01L27/11529 ,  H01L29/423 ,  H01L29/51 ,  H01L21/033 ,  H01L21/321 ,  H01L21/308 ,  H01L21/28 ,  H01L27/11575 ,  H01L27/1157 ,  H01L27/11573

Abstract: Some embodiments of the present application are directed towards an integrated circuit (IC). The integrated circuit includes a semiconductor substrate having a peripheral region and a memory cell region separated by an isolation structure. The isolation structure extends into a top surface of the semiconductor substrate and comprises dielectric material. A logic device is arranged on the peripheral region. A memory device is arranged on the memory region. The memory device includes a gate electrode and a memory hardmask over the gate electrode. An anti-dishing structure is disposed on the isolation structure. An upper surface of the anti-dishing structure and an upper surface of the memory hardmask have equal heights as measured from the top surface of the semiconductor substrate.

公开(公告)号：US20200058664A1

公开(公告)日：2020-02-20

申请号：US15998422

申请日：2018-08-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Wei Cheng Wu ,  Chih-Pin Huang

IPC: H01L27/11548 ,  H01L27/11524 ,  H01L29/423 ,  H01L21/768 ,  H01L21/033 ,  H01L23/532 ,  H01L29/66 ,  H01L21/321 ,  H01L21/762

Abstract: Various embodiments of the present application are directed to an embedded memory boundary structure with a boundary sidewall spacer, and associated forming methods. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A memory cell structure is formed on the memory region and a dummy structure is formed on the isolation structure. A boundary sidewall spacer is formed covering the dummy structure. A protecting dielectric layer is formed on a top surface of the boundary sidewall spacer. The boundary sidewall spacer and the protecting dielectric layer provide a smooth boundary sidewall that is not subject to damage during formation of the logic device structure and, hence, is not subject to trapping high κ etch residue during formation of the logic device structure with HKMG technology.

公开(公告)号：US20200020601A1

公开(公告)日：2020-01-16

申请号：US16578303

申请日：2019-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Ya-Chen Kao ,  Chen-Chin Liu ,  Chih-Pin Huang

IPC: H01L21/66 ,  H01L27/11529 ,  H01L27/11524

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.